1. 1
© Synopsys 2013
Marco Casale-Rossi
Synopsys, Inc.
Advanced Design Implementation
Regardless of Process Technology

2. 2
© Synopsys 2013
Advanced Design, 1980
The Mead & Conway Revolution
“As a result of improvements in
fabrication technology, Large Scale
Integrated (LSI) electronic has became
so dense that a single silicon LSI chip
may contain tens of thousands of
transistors. Many LSI chips, such as
microprocessors, now consist of
multiple, complex subsystems, and thus
are really integrated systems rather than
integrated circuits.
What we have seen so far is only the
beginning. […] It will eventually be
possible to fabricate chips with
hundreds of times as many components
as today’s.”
Source: C. Mead, L. Conway, Introduction to VLSI Systems, 1980

3. 3
© Synopsys 2013
Advanced Design, 2013
We Can Design Chips with Tens of Thousands Times
More Transistors than in 1980,

4. 4
© Synopsys 2013
Advanced Design, 2013
We Can also Mix and Match
Logic + Analog & Mixed-Signal + RF +
Source: Fabless, 2011 (180 & 65 Nanometers Mixed-Signal)

5. 5
© Synopsys 2013
Advanced Design, 2013
Emerging (“More of Moore”) vs.
Established (“More than Moore”) Technology Nodes

6. 6
© Synopsys 2013
0%
5%
10%
15%
20%
25%
30%
> 350 350 250 180 130 90 65/55 45/40 32/28 22/20 16/14 < 14
Worldwide
0%
5%
10%
15%
20%
25%
30%
> 350 350 250 180 130 90 65/55 45/40 32/28 22/20 16/14 < 14
Worldwide
0%
5%
10%
15%
20%
25%
30%
> 350 350 250 180 130 90 65/55 45/40 32/28 22/20 16/14 < 14
Worldwide
86%
(20%)
34%
(66%)
Advanced Design, 2013
Design Starts, Established vs. Emerging Technology Nodes
Source: IBS, Design Starts, 2012
(14%)

7. 7
© Synopsys 2013
Advanced Design, 2013
A Different View: Installed Wafer Capacity Split
Emerging vs. Established Technology Nodes
Source: IC Insights, April 2013

8. 8
© Synopsys 2013
Advanced Design, 2013
We See a Split
• The Emerging Technology Nodes
– Non-planar CMOS at 22nm (Intel) & 14nm (foundries)
– Double patterning at 20nm, triple patterning ahead
– Complex, high volume chips: microprocessors, high-
end graphics, FPGA, wireless SoC
• The Established Technology Nodes
– A lot is done today in larger geometries
– 45/40nm and 28nm are expected to have long lives
– Key applications rely on them
– SoC can be complemented by 2.5D & 3D-IC, MEMS,
etc., enabling a longer technology lifespan

9. 9
© Synopsys 2013
Advanced Design, 201x
Explore, Analyze, then Implement
RTL
Physical
Exploration
Stage
Implementation
Stage
Block
Feasibility
Block
Implementation
RTL
Exploration
RTL
Synthesis
Design
Exploration
Design
Planning

10. 10
© Synopsys 2013
Look-Ahead & Physical Guidance
1 Mx, 2 My, and 2 Mz (Almost Only P&G)
> 80% Routing Utilization, > 10% Smaller Die
DC-T + ICC not Routable DC-G + ICC Routable
Source: IDM, 2013 (130 Nanometers Mixed Signal)

11. 11
© Synopsys 2013
Look-Ahead & Physical Guidance
“Advanced Design Flow for LPDDR2 Non Volatile
Memory Design”
Source: Micron Technology, SNUG France 2012 (180 Nanometers PCM)

12. 12
© Synopsys 2013
Advanced Design, 201x
Analyze, Verify, Guide & Repair as You Implement
Implementation
Sign-Off
P&R STA,
DRC,
Repair
Analyze,
Verify, Guide
Repair
Analyze,
Verify, Guide
Repair
Analyze,
Verify, Guide

13. 13
© Synopsys 2013
Timing Closure
Setup Violations Reduction Across Releases
Baseline 2010.03 = 0%, 130, 90 & 65 Nanometer Designs
Source: Synopsys Research, 2013
Designs with lesser number of violations (< 100) are not included in this chart

14. 14
© Synopsys 2013
Timing Closure
Setup Violations Reduction Across Releases
Baseline 2010.03 SPG = 0%, 130, 90 & 65 Nanometer Designs
Source: Synopsys Research, 2013
Designs with less number of violations (< 100) are not included in this chartDesigns with lesser number of violations (< 100) are not included in this chart

15. 15
© Synopsys 2013
Much More Than Interoperability
In-Design Rail Analysis Detected a Resistance Issue
(4 Instead of 1 ) in the Analog Pre-Routing
Source: IDM, 2012 (90 Nanometers Mixed Signal)

16. 16
© Synopsys 2013
Much More Than Interoperability
In-Design Rail Analysis Detected a Voltage Drop and a
Ground Bounce Issue
Source: IDM, 2012 (65 Nanometers)

17. 17
© Synopsys 2013
Advanced Design, 201x
A Great Deal of Low Power Techniques
Methodology Effectiveness
Multi-Voltage Islands 1.2 – 2.5X
Multi-Voltage Supplies 1.3 - 2X
Lower VDD Operation 1.3 - 5X ( )
MTCMOS (Power Gating) 30 - 120X
VTCMOS (Biasing) 2 – 1.05X ( )
Multi-VTH Optimization 2 - 5X
Clock Gating 1.3 - 2X
Clock Tree Synthesis 1.4 – 3.3X
Multi-Channel Optimization 2 – 5X
DVFS/AVS 1.4 – 2X

18. 18
© Synopsys 2013
Power Management
12 Voltage Islands at 180 Nanometers
Advanced Implementation Technology Helps a Lot
Source: STMicroelectronics, SNUG France 2012 (180 Nanometers Mixed-Signal)

19. 19
© Synopsys 2013
Leakage Power Reduction
The Flow Advantage
Source: Synopsys Research, 2013

20. 20
© Synopsys 2013
Leakage Power Reduction
The Flow Advantage
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
baseline PT only FSLR+PT ICC+FSLR+PT DC+ICC+FSLR+PT
gsp_fp
mscore
DSS_28nm
Pwr % avg
-33%
Fair -42%
Good -50%
Better
-59%
Best
Source: Synopsys Research, 2013
Block 1
Block 2
Block 3

21. 21
© Synopsys 2013
The Flow Advantage
Main Contributors to the 59% Leakage Reduction
Source: Synopsys Research, 2013
DC
28%
(48%)
ICC + FSLR
26%
(43%)
PT
5%
(9%)

22. 22
© Synopsys 2013
The Flow Advantage
Today Design Implementation Technology
to the Rescue of Ten Year Old Process Technology
Block A Block G
Original Leakage (mW) 1X 1X
Original HS Cells (#) 100% 100%
Original LL Cells (#) 0% 0%
Final Leakage (mW) 0.375X 0.527X
Final HS Cells (#) 26.9% 40.3%
Final LL Cells (#) 73.1% 59.7%
Leakage Reduction (%) 62.5% 47.3%
Source: IDM, 2013 (130 Nanometers Mixed Signal)

23. 23
© Synopsys 2013
Advanced Design, 201x
Besides Digital, Analog & Mixed Signal
Place & Route Custom Layout Round-Trip
Source: IDM, 2012 (180 Nanometers Mixed Signal)

24. 24
© Synopsys 2013
Much More Than Interoperability
Place & Route Custom Layout Round-Trip
Analog Routing in Custom Layout Environment
Source: IDM, 2012 (180 Nanometers Mixed Signal)

25. 25
© Synopsys 2013
Much More Than Interoperability
Place & Route Custom Layout Round-Trip
Digital Routing in Place & Route
Source: IDM, 2012 (180 Nanometers Mixed Signal)

26. 26
© Synopsys 2013
Much More Than Interoperability
Analog Pre-Routing & Shielding
Integrity Analysis & Resistance Calculation
Source: IDM, 2012 (90 Nanometers Mixed Signal)

27. 27
© Synopsys 2013
Advanced Design, 201x
Beyond IC, Towards Heterogeneous Systems
Today... Tomorrow
13 x 13 x 2mm
Source: iNEMO-M1, STMicroelectronics, 2012
Note: These Examples Are for Illustration Purposes Only

28. 28
© Synopsys 2013
Heterogeneous Systems
Will Enhance the Performance and Breadth of Solutions
Provided by IC Vendors
Courtesy of A. Fontanelli, Monozukuri, 2012
Package Substrate

29. 29
© Synopsys 2013
Leveraging Existing Tools
Silicon Interposer (Detail) Routed
Source: Synopsys Research, 2011

30. 30
© Synopsys 2013
A New Router
Die-to-Die (µBump to µBump) 45° RDL Routing
Not Only for 3D-IC
Source: Synopsys Research, 2012

31. 31
© Synopsys 2013
Leveraging Existing Tools
Multi-Technology Simulation
X<instance_name> <interconnect> [<module_label>::]<subcircuit_name> <parameters>
.module <label>
.include <>
.lib <>
.model <>
.param <>
.option scale <>
.endmodule

32. 32
© Synopsys 2013
.module memorycube
.lib ‘CMOS28.lib’
.temp 85
.subckt memory1 N1
.ends
.endmodule
Multi-Technology Simulation
Not Only for 3D-IC
X1 N1 memorycube::memory1
X2 N2 logicdie::logic1
X3 N3 analogdie::analog1
V1
.tran 1n 100n
.print v(*)
.module analogdie
.lib ‘CMOS130.lib’
.temp 40
.subckt analog1 N1
.ends
.endmodule
.module logicdie
.lib ‘CMOS20.lib’
.temp 125
.subckt logic1 N1
.ends
.endmodule

33. 33
© Synopsys 2013
Three Years Ago
Use of Routing Resources Across Releases
Baseline = 2007.03, 130 & 90 Nanometer Designs
Design A, 90 Nanometers
Release
Baseline = 6 layers Routability in 5 layers
# routing
Violationspost ICC
% change in area
%change in net
count
%change in wire
length
# routing
Violationspost
ICC
% change in
area
%change in net
count
%change in
wire length
2007.03 4 100.0% 100.0% 100.0% 4582 100.0% 100.0% 100.0%
2007.12 0 99.0% 100.8% 99.0% 2769 98.8% 100.8% 98.9%
2008.09 0 98.4% 102.0% 94.3% 1947 98.1% 101.6% 93.0%
2009.06 0 97.0% 103.6% 89.8% 511 96.9% 103.5% 90.2%
2010.03 6 94.4% 100.3% 82.4% 23 94.1% 100.0% 81.8%
Design B, 90 Nanometers
Release
Baseline = 5 layers Routability in 4 layers
# routing
Violationspost ICC
% change in area
%change in net
count
%change in wire
length
# routing
Violationspost
ICC
% change in
area
%change in net
count
%change in
wire length
2007.12 5 100.0% 100.0% 100.0% 237 100.0% 100.0% 100.0%
2008.09 3 95.1% 92.2% 97.8% 4 96.0% 92.3% 106.4%
2009.06 3 91.6% 88.7% 87.6% 11 91.5% 88.5% 86.5%
2010.03 7 91.7% 92.6% 88.4% 221 93.3% 91.6% 115.7%
Design 3, 130 Nanometers
Release
Baseline = 6 layers Routability in 5 layers
# routing
Violationspost ICC
% change in area
%change in net
count
%change in wire
length
# routing
Violationspost
ICC
% change in
area
%change in net
count
%change in
wire length
2007.12 0 100.0% 100.0% 100.0% 65792 100.0% 100.0% 100.0%
2008.09 0 99.4% 105.9% 106.3% 75162 100.5% 108.1% 111.8%
2009.06 7 97.8% 103.4% 94.8% 71154 95.9% 102.4% 95.1%
2010.03 26 94.8% 94.4% 96.4% 35835 94.0% 93.8% 92.3%
Source: Synopsys Research, 2010

34. 34
© Synopsys 2013
Today
Use of Routing Resources Across Releases
Baseline = 2010.03, 130 & 65 Nanometer Designs
Design
Name
Baseline =
Routing Violations
Using 8 layers
Routing Violations
Using 6 Layers
Routing Violations
Using 5 Layers
2010.03 2010.12 2011.09 2012.06 2013.03 2010.03 2010.12 2011.09 2012.06 2013.03 2010.03 2010.12 2011.09 2012.06 2013.03
Design 2 14 34 20 38 29 23 15 18 12 3 8460 6397 3508 4743 3301
Design 3 135 117 112 119 130 120 116 125 120 116 560 112 106 107 117
Design 8 2341 2038 2326 2223 2446 2692 2400 2587 2697 3099 3715 2911 3464 4202 3918
Design 9 2460 2400 2159 2617 2490 2626 2706 2443 2711 2596 5425 5760 6305 7598 6050
Design 10 25 12 28 15 15 43 40 12 28 17 27267 13274 809 15423 1534
Source: Synopsys Research, 2013

35. 35
© Synopsys 2013
Use Of Routing Resources
3 Layers Instead of 4
Utilization from 60% to 67%, 81% Double Via Rate
Source: IDM, 2012 (130 Nanometers Mixed Signal)

36. 36
© Synopsys 2013
Use Of Routing Resources
4 Layers Instead of 6
Utilization 77%, 80% Double Via Rate
DC-G + ICC Routable
Source: IDM, 2012 (130 Nanometers Mixed Signal)

37. 37
© Synopsys 2013
• Technologies look like “trailing edge” from a manu-
facturing process point-of-view
• Design, instead, is “bleeding edge” regardless of the
manufacturing process, and will even more THE
differentiator
• EDA is a critical ingredient of successful design
• The final result of combining “more than Moore” and
“more of Moore” can be surprisingly more advanced than
what is allowed by the simple progression of the
semiconductor roadmap through scaling
Conclusions
Source: C. Cognetti, STMicroelectronics, Napa KGD Packaging & Test 2004

38. 38
© Synopsys 2013
Follow Synopsys!
facebook.com/synopsys
twitter.com/synopsys youtube.com/synopsys
linkd.in/MThWJg

39. 39
© Synopsys 2013
‫ה‬ ָ‫ּתֹוד‬
May 2nd, 2013
Tel Aviv, Israel