2014 Hardware Based IEEE Projects in VLSI
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2014 Hardware Based IEEE Projects in VLSI
- 1. VLSI Email: vlsi@pantechmail.com www.finalyearieeeprojects.com| www.pantechsolutions.net | www.pantechproed.com 12 ©2013 Pantech ProEd Private Limited PROJECT CODE PROJECT THEME APPLICATION TECHNOLOGY / CORE PSVLS301 Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays Avionics IEEE2013 TESTING|DFT CMOS|MEMORY DESIGN PSVLS302 LFSR-Reseeding Scheme For Achieving Test Coverage Cellular Telephony PSVLS303 DC Noise Margin and Failure Analysis of Proposed Low Swing Voltage SRAM cell for High Speed CMOS Circuits Microchip Manufacturing PSVLS304 Used self-controllable Voltage Level technique to reduce leakage current in DRAM 4×4 in VLSI Microchip Manufacturing PSVLS305 Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic Photovoltaics IEEE2013 CADENCE LOWPOWERDESIGN|CMOS|SEQUENTIAL,ARITHMETIC,DIGITALANDANALOGCIRCUITS PSVLS306 Logical Effort for CMOS-Based Dual Mode Logic Gates Microchip Manufacturing PSVLS307 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme Photovoltaics PSVLS308 Low-power high-speed full adder for portable electronic applications MEMS PSVLS309 Low-Power Digital Signal Processing Using Approximate Adders Power Management PSVLS310 Activity-Driven Fine-grained Clock Gating and Run Time Power Gating Integration Microchip Manufacturing PSVLS311 A Novel Flip-Flop Design for Low Power Clocking System Avionics PSVLS312 Modeling and Simulation of Low Power 14 T Full Adder with Reduced Ground Bounce Noise at 45 nm Technology Microchip Manufacturing PSVLS313 Leakage Minimization of 10T Full Adder Using Deep Sub-Micron Technique Microchip Manufacturing PSVLS314 Asynchronous Design of Energy Efficient Full Adder Photovoltaics PSVLS315 Design of a Low-Power Pulse-Triggered Flip-Flop with Conditional Clock Technique RF & MEMS PSVLS316 Design of High Speed and Low Power 15-4 Compressor Avionics PSVLS317 Analysis and design of a Low-Voltage Low-Power Double-tail Comparator Avionics PSVLS318 Comparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm Technology Avionics PSVLS319 Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop Photovoltaics PSVLS320 Comparative Analysis For Hardware Circuit Architecture Of Wallace Tree Multiplier Microchip Manufacturing PSVLS321 Rescue robo Machine Vision PSVLS322 License Plate Recognition For Toll Gate System Electronic Article Surveillance PSVLS323 Improved number plate localization algorithm and its efficient field programmable gate arrays implementation Electronic Article Surveillance
- 2. VLSI Email: vlsi@pantechmail.com www.finalyearieeeprojects.com| www.pantechsolutions.net | www.pantechproed.com 13 ©2013 Pantech ProEd Private Limited PSVLS324 Prototype of a Fingerprint Based Licensing System For Driving Machine Vision IEEE2013 SPARTAN3AN REAL-TIMEAPPLICATONS(GPS,GSM,ZIGBEE, RF) PSVLS325 Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location Sensing Machine Vision PSVLS326 Secure Transmission in Downlink Cellular Network with a Cooperative Jammer Signal Jamming PSVLS327 A Smarter Toll Gate Based on Web Of Things Electronic Article Surveillance PSVLS328 An Interactive RFID-based Bracelet for Airport Luggage Tracking System Asset Tracking PSVLS329 RFID-based Location System for Forest Search and Rescue Missions Machine Vision PSVLS330 Design and Implement of Real-time Monitoring System of Urban Water Supply Remote Monitoring PSVLS331 FPGA Based Embedded Webserver Using Microblaze Processor Automotive Infotainment IEEE2013 SPARTAN6 EDK|SOFTCOREPROCESSORDESIGN PSVLS332 Exploration of Multi-thread Processing on XILKERNEL for FPGA Based Embedded Systems Automotive Infotainment PSVLS333 Energy Efficient Image Transmission Machine Vision PSVLS334 Fast FPGA-Based Multi-object Feature Extraction Computer Vision PSVLS335 “ i ” - A novel algorithm for Optical Character Recognition (OCR) Vehicular Networking PSVLS336 Hardware Implementation of a Digital Watermarking System for Video Authentication Defence PSVLS337 Reconfigurable Processor for Binary Image Processing Machine Vision PSVLS338 FPGA Implementation of Pipelined Architecture For SPIHT Algorithm Biomedical Signal PSVLS339 Least Significant Bit Matching Steganalysis Based on Feature Analysis Defence PSVLS340 Implementation of I2C Master Bus Controller on FPGA Networking Line Card IEEE2013 COMMUNICATION PROTOCOLDESIGN PSVLS341 Pipelined Radix-2K Feed forward FFT Architectures Radar PSVLS342 Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT OFDM PSVLS343 High-Throughput Compact Delay-Insensitive Asynchronous NoC Router Computer Networking PSVLS344 Design of Sobel Operator Using Field Programmable Gate Arrays Machine Vision IEEE2013 SPARTAN6 BIOMEDICAL PSVLS345 Modified Gradient Search for Level Set Based Image Segmentation Bio-Medical PSVLS346 Selective Eigen background for Background Modeling and Subtraction in Crowded Scenes Computer Vision
- 3. VLSI Email: vlsi@pantechmail.com www.finalyearieeeprojects.com| www.pantechsolutions.net | www.pantechproed.com 14 ©2013 Pantech ProEd Private Limited PSVLS347 FPGA Implementation of Moving Object Detection in Frames by Using Background Subtraction Algorithm Computer Vision IEEE2013 SPARTAN6 BIOMEDICAL PSVLS348 Realization of Beamlet Transform Edge Detection Algorithm using FPGA Computer Vision PSVLS349 An Analysis of SOBEL and GABOR Image Filters for Identifying Fish Machine Vision PSVLS350 Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT Computer Vision IEEE2013 SPARTAN6 NONLINEARFILTERS PSVLS351 Optical Flow Estimation for Flame Detection in Videos Computer Vision PSVLS352 An Efficient Denoising Architecture for Removal of Impulse Noise in Images Computer Vision PSVLS353 Design and Implementation of Hardware Architecture for Denoising Using FPGA Computer Vision PSVLS354 Performance Analysis of Encryption Algorithms for Information Security Defence IEEE2013 NETWORKSECURITY PSVLS355 Exploiting Vulnerabilities in Cryptographic Hash Functions Based on Reconfigurable Hardware NSA Products PSVLS356 Parallel AES Encryption Engines for Many-Core Processor Arrays NSA Products PSVLS357 FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial using VHDL Microchip Manufacturing IEEE2012 TESTING LOWPOWERDESIGNCIRCUITS|TANNEREDAS-EDIT&W-EDIT PSVLS358 Optimization of Microcode Built-In Self Test By Enhanced Faults Coverage for Embedded Memory Microchip Manufacturing PSVLS359 Low-Power and Area-Efficient Carry Select Adder Power Management PSVLS360 Designing and Simulation of Full Adder Cell Using FINFET Technique Avionics PSVLS361 A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS Technique Avionics PSVLS362 A Low Power CMOS Voltage Mode SRAM Cell for High Speed VLSI Design Microchip Manufacturing PSVLS363 Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme Photovoltaics PSVLS364 Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks MEMS PSVLS365 Ultralow-Voltage Process-Variation-Tolerant Schmitt- Trigger-Based SRAM Design Microchip Manufacturing PSVLS366 Single Phase Clocked Quasi Static Adiabatic Tree Adder Photovoltaics PSVLS367 An Embedded Real-Time Finger-Vein Recognition System for Mobile Devices Machine Vision IEEE2012 BIOMETRIC WSN PSVLS368 Gesture Recognition Using Field Programmable Gate Arrays Machine Vision PSVLS369 An improved three-factor authentication scheme using smart card with biometric privacy protection Machine Vision PSVLS370 Platform-Independent Customizable UART Soft-Core Modems
- 4. VLSI Email: vlsi@pantechmail.com www.finalyearieeeprojects.com| www.pantechsolutions.net | www.pantechproed.com 15 ©2013 Pantech ProEd Private Limited PSVLS371 BPSK System on Spartan 3E FPGA WLAN, , Bluetooth IEEE2012 SIGNALPROCESSING COREPROCESSORDESIGN|CRYPTOGRAPHY PSVLS372 Design of an error detection and data recovery architecture for motion estimation testing applications Computer Vision PSVLS373 Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation Radar PSVLS374 Real Time Communication between Multiple FPGA Systems in Multitasking Environment Using RTOS Automotive Infotainment PSVLS375 Analysis of CT and MRI Image Fusion using Wavelet Transform Bio-Medical PSVLS376 A Level Set Based Deformable Model for Segmenting Tumors in Medical Images Machine Vision PSVLS377 Edge Detection of Angiogram Images Using the Classical Image Processing Techniques Machine Vision PSVLS378 FPGA Hardware of the LSB Steganography Method Defence PSVLS379 An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion Computer Vision PSVLS380 An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform Biomedical PSVLS381 A Level Set Based Deformable Model for Segmenting Tumors in Medical Images Biomedical PSVLS382 A Novel Architecture for VLSI Implementation of RSA Cryptosystem Defence PSVLS383 An efficient FPGA implementation of the Advanced Encryption Standard Algorithm NSA Products PSVLS384 A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL NSA Products