Pdc lab manualnew

PDC lab manual ACE engineering college Dept. ECE
1
ACE
Engineering College
Ankushapur(V), Ghatkesar(M), R.R.Dist - 501 301.
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
PULSE AND DIGITAL CIRCUITS
LAB MANUAL
Prepared by:
D V S Ramanjaneyulu
Assistant Professor
anji.dvsr@gmail.com
ramanjaneyuludvsr.ece@aceec.ac.in

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Experiment: 1a
LINEAR WAVE SHAPING
Aim:-
: Design a RC LPF and HPF at various time constants and verify the
Responses for Square wave input (choose C = 0.1f, Vi = 4 VP-P, f = 1 K Hz).
Pre lab:-
1. Study the working of RC low pass & high pass circuits & their responses.
2. Draw the circuit diagram for RC high pass &low pass circuits.
3. Draw the expected waveforms under different time constants.
Objective::
1. To design High pass and Low pass RC circuits for different time constants and verify their responses for a
square wave input of given frequency.
2. To find the % tilt of high pass RC circuit for large time constant.
3.To study the operation of high pass RC circuit as a differentiator and low pass circuit as an integrator.
Apparatus:-
1. CRO
2. Signal Generator
3. Bread board
4. Capacitor( 0.1f )
5. Resistors (1K, 10 K ,100 K)
Circuit Diagram:-
Low Pass Filter:

3
a) RC = T
C = 0.1f, R = 10K
V
e
e
V
V
RC
T
RC
T
49.0
1
1
2
2
2
2 




 




 
 V1 = -0.49 V
a) RC=T
b) RC >> T
R = 100 K, C = 0.1 f
V
e
e
V
V
RC
T
RC
T
05.0
1
1
2
2
2
2 




 




 
 V1= 0.05v

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c) RC << T
R = 1k,,
C = 0.1 f
Model graph
Note:
Low Pass Filter allows the DC component of I/P signal and High Pass Filter block the DC component of I/P
Signal.
High Pass Filter:
Design / Calculations: a) RC = T
Given T = 1/10 KHz = 0.1 msec
R = 0.1x 10-3
/ 0.1f = 10k
V1 = V / (1 + e-T/2RC
) = 2.49 V
V
e
V
V
RC
T
51.1
1 2
|
1 


2
%
|
11
V
VV
tilt

 = (2.49 – 1.51)/2 = 49%)

5
RC=T
T1 = T2 = T/2
b) RC >> T
Choose RC = 10T = 1 mSec
R = 100k
The O/P waveform will be identical to I/P
T1 = T2 = T/2
c) RC << T
RC = 0.1 T
R = 1k

6
Procedure:-
1. Connect the circuit as shown in figure (LPF / HPF)
2. Apply the Square wave input to this circuit ( Vi = 4 VP-P, f = 10KHz)
3. Observe the output waveform for (a) RC = T, (b) RC>>T, (c) RC>>T
4. Verify the values with theoretical calculations
5. To obtain the frequency response apply the sine wave input to the RC High pass circuit ( Vi = 4 VP-P, f =
1KHz). Now vary the frequency and note down the o/p amplitude. Calculate the gain in db and plot the
graph between frequency vs gain in db and calculate the cutoff frequency and verify it with theoretical
value
6. Repeat the step 5 for RC Low pass circuit.
Observations :
Low Pass RC circuit
S.No. Time
Constant
Voltage levels
Theoritical
Practical
1. RC=T V1
V2
2. RC>>T V1 `
V2
3. RC<<T V1
V2

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High Pass RC circuit
S.No. Time
Constant
Voltage levels
Theoritical Practical
1. RC=T V1
V1
1
V2
V2
1
% Tilt
2. RC>>T V1
V1
1
V2
V2
1
% Tilt
3. RC<<T V1
V1
1
V2
V2
1
% Tilt
Post lab:-
1. Tabulate the percentage tilt of RC high pass circuit under different time constants& compare the responses.
2. Tabulate the rise time of RC low pass circuit& compare the responses
3. Compare the practical results with theoretical results.
4. Write the conclusion & results
Precautions:
Use two CRO probes and observe I/P & O/P waveforms simultaneously by putting CRO on DC modes.

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Result:-
LPF and HPF is designed at various time constants and the responses for square wave input is observed & hence plotted.
Viva questions
1. What is a linear network? What is linear wave shaping?
2. Define Time constant. What is its formula?
3. Define % tilt and rise time. Write the expressions for the same.
4. When High pass RC circuit is used as Differentiator? What is the formula for the output, when operated
as differentiator?
5. When Low pass RC circuit is used as Integrator? What is the formula for the output, when the circuit is
operated as Integrator?
6. What is the Difference between Low pass and High pass RC circuits.
7. A Capacitor blocks __ signal and passes __ signal. The voltage across the ___ will not change
suddenly.
8. Explain 3 dB values for a LP and HP circuit.
9. A differentiator converts a square wave into what form? An integrator converts a square wave into what
form?
10. What are the formulae for charging a capacitor from an initial voltage of Vi to a final voltage of Vo.
11. Instead of using RC components for a low pass or high pass, how the circuit changes , if we want to use
RL components? What are the values for the Time constant for RL circuits?
12. When a capacitor in a low pass circuit charges to 99.3 % ( treated as fully charged) for a step input to
a Low pass filter?
13. What is a peaking circuit?
14. What is a ringing circuit?
15. Why resistive attenuators are to be compensated?
Design Problems
1. Design RC Differentiator circuit for frequency of 2kHz.
2. Design RC high circuit for a square wave input signal of frequency 2.5KHz for
i) RC=10T ii)RC=T iii)RC=T/10
3. Design low pass circuit for a square wave signal of 3KHz for
i) RC=5T ii) RC=T iii) RC = T/5
4. Verify the output of circuits given in Fig1.1 and Fig 1.2 for input square wave of frequencies 10KHz and
500Hz.
5. Verify the RC high pass circuit output for sinusoidal input.
Outcomes:
After finishing this experiment the students are able to
1. Design High pass and Low pass circuits with different time constants.
2. Find % Tilt
3. Observe the output waveforms for a given square wave.

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Experiment: 2.a
NON-LINEAR WAVE SHAPING
Aim:-
a) To study the Transfer characteristics and response of clippers
(i) Positive and Negative Clippers
(ii) Clipping at two independent levels
Pre lab:-
1. Study the working of clipping circuits& their responses.
2. Study the data sheet of IN 4007 diode.
3. Draw the circuit diagrams for various clippers.
4. Draw the expected waveforms
Objective:
1. To study the various clipper circuits and to plot the output waveforms for a sinusoidal input of given peak
amplitude.(Choose f=1 kHz, Vp-p =10v)
2. To observe the transfer characteristics of all the clipping circuits on CRO.
Apparatus:-
1. Signal Generator.
2. Bread board
3. Connecting patch cards.
4. CRO
5. DC power supply (dual)
6. Resistors (2.2K)
7. Diodes (1N4007)
Theory:-
Clipping circuits basically limit the amplitude of the input signal either below or above certain voltage level.
They are referred to as Voltage limiters, Amplitude selectors or Slicers. A clipping circuit is one, in which a small
section of input waveform is missing or cut or truncated at the out put section.
Clipping circuits are classified based on the position of Diode.
1.Series Diode Clipper
2.Shunt Diode Clipper
Procedure:-
1. Connect the circuit as shown in fig.1
2. In each case apply 10 VP-P, 1KHz Sine wave I/P using a signal generator.
3. Observe the O/P waveform on the CRO in comparison with I/P waveform.
4. Sketch the I/P as well as O/P waveforms and mark the numerical values.
5. Note the changes in the O/P due to variations in the reference voltage VR = 2V, 3V.
6. O/P is taken across the load RL.
7. Obtain the transfer characteristics of Fig.1, by keeping CRO in X-Y plane.
8. Repeat the above steps for all the figures.

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Precautions:
1. Set the CRO O/P channel in DC mode always.
2. Observe the waveform simultaneously by keeping common ground.
3. See that there is no DC component in the I/P.
4. To find transfer characteristics apply input to the X-Channel, OP to Y-Channel, adjust the dot at the center
of the screen when CRO is in X-Y mode. Both the channels modes must be in ground, then remove
ground and plot the transfer characteristics.
Input Waveform:
Series Diode clippers
CIRCUIT DIAGRAM O/P WAVEFORMS

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Shunt diode clippers
Series diode clipper with bias

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Shunt diode clipper with bias
(i) Slicer (Clipping at two independent levels)
Observations:
S. No. Type of Clipper Reference Practical
Voltage Clipping Voltage levels
0V V1
1 Series Positive Clipper
V2
2V V1
V2
0V V1
2 Series Negative Clipper
V2
2V V1
Series Negative Clipper
V2

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0V V1
3 Shunt Positive Clipper
V2
2V V1
V2
0V V1
4 Shunt Negative Clipper
V2
2V V1
V2
5 Two level clipper
V1
V2
Post lab:-
1. Observe the response of the various clipping circuits.
2. Compare the results with model graphs.
3. Observe the amount of clipping for a given input.
4. Write the conclusions and results.
Result:-
Different types of clipping circuits have been studied and observed the responses for various combinations of
VR and clipping diodes.
Viva Questions:
1. Define non linear wave shaping? What are the non-linear components?
2. Define clipping circuit? What are the other names for clippers?
3. Write the piecewise linear characteristics of a diode?
4. What are the different types of clippers?
5. Which kind of a clipper is called a slicer circuit?
6. What are the applications of Clipper Circuits?
7. What is the figure of merit for diodes used in clipping circuits?
8. What is the influence of the practical diode compared to the ideal diode, in the above circuits?

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9. Instead of sinusoidal wave form as input, if we give other wave forms like triangular or square, then how the
clipping action is performed?
10. What is Vγ for Ge diode and Vγ for Si diode?
Design Problems
1. Design a clipper circuit to get the output shown in below for a sinusoidal input with 10V peak to peak.
2. Design a clipper circuit using zener diode with 4.7V break down voltage.
3. Verify the output of clipper circuit for square & triangular inputs.
Outcomes: After finishing this experiment, students are able to design different types of clipper circuits and observe
the input – output waveforms in the CRO and obtain the transfer characteristics for each circuit.

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Experiment: 2.b
NON-LINEAR WAVE SHAPING
Aim:-
(b) To study the steady state output waveform of Clampers for a square wave input
(i) Positive and Negative Clamper
(ii) Clamping at reference levels
Pre lab:-
1. Study the working of clamping circuits.
2. Study the data sheet of IN 4007 diode.
3. Draw the circuit diagrams for various clampers.
4. Draw the expected waveforms
Objective:-
l. To study the various clamping circuits and to plot the output waveforms for a sinusoidal input of given peak
amplitude. (Choose f=l KHz, Vp-p =l0 V)
Apparatus:-
1. Signal Generator.
2. Bread board
4. CRO
5. DC power supply (dual)
6. Resistors ( 100 K )
7. Diodes (1N4007)
8. Capacitor (0.1f)
Theory:-
The process where sinusoidal signals are going to be altered by transmitting through a non-linear network is
called non-linear wave shaping. Non-linear elements (like diodes) in combination with resistors and capacitors can
function as clamping circuit
Clamping circuits add a DC level to an AC signal. A clamper is also refer to as DC restorer or DC re-
inserter. The Clampers which clamp the given waveform either above or below the reference level, which
are known as positive or negative clamping respectively.
Clamping circuits are classified as two types.
i) Negative Clampers ii) Positive Clampers
Procedure:-
1. Connect the circuit as shown
2. Apply a Sine wave of 10VP-P, 1KHz at the input terminals with the help of Signal Generator.
3. Observe the I/P & O/P waveforms of CRO and plot the waveforms and mark the values with VR = 2 V,
3V

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4. O/P is taken across the load RL.
5. Repeat the above steps for all clamping circuits as shown.
6. Waveforms are drawn assuming diode is ideal.
Input Waveform:-
Positive clamping with zero reference voltage
Negative clamping with zero reference voltage
t
-5V
Vi =5V

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Positive clamping with +ve reference voltage
Positive clamping with -ve reference voltage
Negative clamping with –ve reference voltage
Negative clamping with +ve reference voltage

18
Observations:
Sl No. Type of Clamper
Reference
Practical clamping reference
Voltage
Voltage levels
0V V1
V2
l Positive Clamper
2V V1
V2
-2V V1
V2
0V V1
V2
2 Negative Clamper
2V V1
V2
-2V V1
V2
Post lab:-
1. Observe the response of the various clamping circuits.
2. Compare the results with model graphs.
3. Observe the clamping for a given reference voltage.
4. Write the conclusions and results.

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Result:-
Different types of clamping circuits are studied and observed the response for different combinations of VR
and diodes.
Viva Questions:-
1. What are the applications of clamping circuits?
2. What is the synchronized clamping?
3. Explain the Principle of operation of Clampers.
4. What is clamping circuit theorem.
5. What is the function of the capacitor in clamper circuit?
6. What are the effects of diode characteristics on the output of the Clamper?
7. If we interchange the diode and the capacitor in fig 1 above, how the circuit behaves?
8. Calculate the power dissipation in the Resistor for any one of the above circuits?
9. What is the difference between a clipper and a clamper?
10. What are the other names for clampers?
Design Problems
1. Design a circuit that clamps the positive peaks to zero that can effectively provide DC restoration to input
with frequency extending up to 1.5KHz.
2. How much voltage will get across capacitor in clamper circuit with input voltage of 20Vp-p
3. Design a negative clamper circuit from positive clamper circuit.
Outcomes: After finishing this experiment students are able to design different types of clamper circuits.

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Experiment: 4
SWITCHING CHARACTERISTICS OF A TRANSISTOR
Aim:-
Design Transistor to act as a Switch and verify the operation. Choose VCC = 10V, ICmax = 10 mA, hfe = 50,
VCESat = 0.2, Vin = 4Vp-p, VBESat= 0.6V
Pre Lab:-
1. Study the working of transistor in saturation & Cutoff region.
2. Study the data sheet of BC107 transistor and note the VCE(sat) & VBE(sat) values
Apparatus:-
1. Transistor (BC 107)
2. Bread board
3. CRO
4. Resistors (1K, 8.2K)
5. DC power supply
6. Function Generator
Theory:-
When the I/P voltage Vi is negative or zero, transistor is cut-off and no current flows through Rc hence V0 
VCC when I/P Voltage Vi jumps to positive voltage, transistor will be driven into saturation.
V0 = Vcc – ICRC  VCESat
Design procedure:-
When Q is ON RC =
maxC
CESatCC
I
VV 
= (10-0.2) / 10 mA = 1K
IB  ICmax / hfe
 10mA / 50
IB 0.2 mA
To keep transistor remain in ON, IB should be greater than
Ibmin = 0.2mA
Vin = IBRB + VBE Sat
2V = 0.2 mA RB + 0.6V
RB = 7 K (choose practical values as 8.2 K)

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Test for cut-off:
Find the Base to Emitter Voltage; VBE is negative for npn cut-off
and positive for pnp cut-off
Test for saturation:
Evaluate collector current IC and the base current IB independently.
If IB> IB(min), where IB(min)= IC/hfe the transistor is in saturation.
Circuit diagram:-
Procedure:-
1. Connect the circuit as shown in figure.
2. Apply the Square wave 4 V(p-p) frequency of 1 KHz
3. Observe the waveforms at Collector and Base and plot it.
4. Repeat same with different frequencies.
Precautions:
1. When you are measuring O/P waveform at collector and base, keep the CRO in DC mode.
2. When you are measuring VBE Sat, VCE Sat keep volts/div switch at either 0.2 or 0.5 position.
3. When you are applying the square wave see that there is no DC voltage in that. This can be checked by
CRO in either AC or DC mode, there should not be any jumps/distortion in waveform on the screen.

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Expected waveforms:-
Post Lab:-
1. Tabulate results for DC & AC analysis
2. Compare the theoretical values with practical values
3. Draw the graphs for DC & AC analysis.
Result:-
Transistor as a switch has been designed and O/P waveforms are observed.
Viva Questions:-
1. Mention typical values of VBE Sat, VCE Sat for both Si, Ge Transistors?
2. Define ON time and OFF time of the transistor?
3. Define Rise time & fall time of a transistor switch?
4. Define Storage time and delay time?
5. What is the phase difference between the input and the output, when the transistor is conducting?
6. What modifications are to be done in the above circuit if we use PNP transistor instead of NPN transistor?
7. How to calculate IC in the above circuit, when the transistor is ON?
8. What is the output voltage swing for the above circuit?
9. Why square wave is given as input instead of a sinusoidal wave for switching ON and OFF of the transistor?
10. In which regions Transistor acts as a switch?
Design problem
1. Design transistor switch to get an output of 12Vp-p swing.
2. Can we apply sinusoidal signal to transistor as switch & verify the output for the same.
3. Design a high speed transistor switch.
Outcomes: After finishing this experiment, the students are able to design a transistor switch circuit and
observe the waveforms.

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Experiment: 5
BISTABLE MULTIVIBRATOR
Aim:-
a) Design a Bi-stable Multivibrator circuit and draw its waveforms
b) Obtain the resolving time of Bi-stable Multivibrator and verify theoretically. Choose R1 = 10K, C = 0.3f, VCE Sat =
0.2V, ICmax = 15mA, VCC = 15V,
VBB = 15V, VB1 = -4.8V
Pre Lab:-
1. Study the working of Bi-stable multivibrator.
2. Study the different triggering methods.
3. Study the data sheet.
Apparatus:-
2. CRO
3. Connecting patch cards
4. Resistors
5. Capacitors
Circuit diagram:-
Theory:
A Bistable circuit is one which can exist indefinitely in either of two stable states and which can be induced to make
an abrupt transition from one state to the other by means of external excitation. The Bistable circuit is also called as
Bistable multivibrator, Eccles Jordon circuit, Trigger circuit, Scale-of-2 toggle circuit, Flip-Flop & Binary.
A Bistable multivibratior is used in a many digital operations such as counting and the storing of binary information. It
is also used in the generation and processing of pulse-type waveform. They can be used to control digital circuits and
as frequency dividers.
There are two outputs available which are complements of one another. i.e. when one output is high the other is low
and vice versa .
Operation:
When VCC is applied, one transistor will start conducting slightly more than that of the other, because of some
differences in the characteristics of a transistor. Let Q2 be ON and Q1 be OFF. When Q2 is ON, The potential at the
collector of Q2 decreases, which in turn will decrease the potential at the base of Q1 due to potential divider action of
R1 and R2. The potential at the collector of Q1 increases which in turn further increases the base to emitter voltage at

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the base of Q2. The voltage at the collector of Q2 further decreases, which in turn further reduces the voltage at the
base of Q1. This action will continue till Q2 becomes fully saturated and Q1 becomes fully cutoff.
Thus the stable state of binary is such that one device remains in cut-off and other device remains at saturation. It will
be in that state until the triggering pulse is applied to it. It has two stable states. For every transition of states triggering
is required. At a time only one device will be conducting.
NEED OF COMMUTATING CAPACITORS (SPEED UP CAPACITORS):
It is desired that the transition should take place as soon as the trigger pulse is applied but such is not the case.
When transistor is in active region it stores charge in its base and when it is in the saturation region it stores even
more charge. Hence transistor cannot come out of saturation to cut- off. Until all such charges are removed. The
interval during which conduction transfer one transistor to other is called as the transition
Design:-
RC =
maxC
CESatCC
I
VV 
RC = (15 – 0.2) / 15mA  1K
Choose RC = 1K, VB1 =
21
2
21
1
RR
RV
RR
RV CESatBB




-4.8 =
2
2
10
2.01015
R
Rx


; R2 = 20K
fmax =
21
21
2 RCR
RR 
= KHz
xxx
K
250
20103.02
2010


(=55KHz)
Procedure:-
1. Switch ON the system and observe for the power LED indication.
2. Apply two Square waves with same frequency or different frequency at terminals T1 & T2. you may
observe symmetrical or Asymmetrical square waves respectively. Observe both I/P & O/P
waveforms on CRO.
3. Until you get a 500Hz at the O/P increase the trigger I/P amplitude, note down the amplitude, this is
the minimum pulse step required for trigger the bi-stable Multivibrator with the given circuit
parameters.
4. Now slowly increase the frequency and at one particular frequency the circuit does not respond and
the output disappears. Just lesser than this frequency, the circuit again responds, this is the maximum
allowable frequency.
5. Without applying the trigger input (5V, 1KHz )note down the values at Vb1, Vb2, Vc1 & Vc2. Ensure
that the transistors one is at cutoff and one is in saturation.
6. Apply the trigger pulse 1 KHz square wave using function generator.
7. Sketch the O/P waveforms at Vce1, Vce2 , Vbe1, Vbe2 , with respect to trigger input and the sample O/P
waveforms are as shown in figure.
Vbe1 Vce1 Vbe2 Vce2 Q1 Q2
Before triggering
After triggering

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Expected Waveforms:-
Post lab:-
1. Draw the waveform for VBE , VBE2 ,VCE & VCE2. with respect to triggering signal
Result:-
Bi-stable Multivibrator circuit is designed and output waveforms are observed.
Viva Questions:
1. What are the other names of Bistable Multivibrator?
2. What are the applications of a Bitable Multivibrator?
3. Describe the operation of commutating capacitors?
4. Commutating capacitors are also called as __ or __ .
5. What is the meaning of a stable state in a multi-vibrator?
6. Mention the names of different kinds of triggering used in the circuit shown?
7. What are the disadvantages of direct coupled Binary?
8. The diodes used in a bistable multivibrator to maintain a constant output swing are called __ diodes.
9. The interval during which conduction transfers from one transistor to another is called the __.
10. What are the coupling elements of a Bi-stable Multivibrator?
Design Projects
1. Design a fixed bias binary employing two n-p-n silicon transistor to operate max frequency of 16KHz,
VCC=VBB=10V, IC(sat)=5mA, hfe(min)=30.
2. Design and verify the bistable multivibrator by using different triggering methods.
Outcomes: After finishing this experiment students are able to design Bistable Multivibrator and able to explain its
operation.

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Experiment:6
ASTABLE MULTIVIBRATOR
Aim:-
To design an Astable Multivibrator and draw its waveforms
To generate a Square wave of 1KHz frequency. Choose C = 1nf, 10nf, 100nf.
Pre Lab:-
1. Study the working of astable multivibrator.
2. Study the data sheet of BC107 transistor and note the VCE(sat) & VBE(sat) values.
Objective:
1. To study the operation and observe the wave forms of Astable Multivibrator.
2. To Design an Astable Multivibrator to generate a square wave of 1 KHz frequency using Transistor.
Appartus:-
1. Regulated DC Power supply - 1 no
2. CRO, - 1 no
3. Resistors (1K, 68K) - each 2 no’s
4. Capacitors (0.1f) - 2 no’s
5. Transistors (BC 107) - 2 no’s
Circuit diagram:-
Theory:
The Astable circuit has two quasi-stable states. Without external triggering signal the Astable configuration will make
successive transitions from one quasi-stable state to the other. The Astable circuit is an oscillator. It is also called as
free running multivibrator and is used to generate “Square Wave”. Since it does not require triggering signal, fast
switching is possible.
Operation:
When the power is applied, due to some imbalance in the circuit, the transistor Q2 conducts more than Q1 i.e. current
flowing through transistor Q2 is more than the current flowing in transistor Q1. The voltage VC2 drops. This drop is
coupled by the capacitor C1 to the base by Q1 there by reducing its forward base-emitter voltage and causing Q1 to

27
conduct less. As the current through Q1 decreases, VC1 rises. This rise is coupled by the capacitor C2 to the base of Q2.
There by increasing its base- emitter forward bias. This Q2 conducts more and more and Q1 conducts less and less,
each action reinforcing the other. Ultimately Q2 gets saturated and becomes fully ON and Q1 becomes OFF. During
this time C1 has been charging towards VCC exponentially with a time constant T1 = R1C1. The polarity of C1 should be
such that it should supply voltage to the base of Q1. When C1 gains sufficient voltage, it drives Q1 ON. Then VC1
decreases and makes Q2 OFF. VC2 increases and makes Q1 fully saturated. During this time C2 has been charging
through VCC, R2, C2 and Qi with a time constant T2 = R2C2. The polarity of C2 should be such that it should supply
voltage to the base of Q2. When C2 gains sufficient voltage, it drives Q2 ON, and the process repeats.
Design:-
The period T is given by
T = T1 + T2 = 0.69 (R1C1 + R2C2)
For symmetrical circuit with R1 = R2 = R & C1 = C2 = C
R1 = R2 = R = 68 k and c1 = c2 = c = 0.01µf
T = 1.38 RC
T = 1.38 * 68k * 68k *0.01µ *0.01µ = 0.93ms
Let VCC = 12V; hfe = 51 (for BC107)
VBESat = 0.7V ; VCESat = 0.3V ; f = 1/T = 1.06 khz
Choose ICmax = 10mA,
RC = (VCC – VCESat) / ICmax
= (12 – 0.3) / (10 x 10-3
) = 1.47K  RC  1K
Expected wave form:-

28
Procedure:-
1. Connect the circuit as shown in figure. Apply 12V DC power supply to the circuit.
2. Observe the Base Voltage and Collector Voltages of Q1 & Q2 on CRO in DC mode and plot them.
3. Verify the frequencies theoretically.
Post Lab:-
1. Calculate the time period for astable multivibrator.
2. Compare the practical value of time period with theoretical value.
3. Draw the graph for VBE , VBE2 ,VCE & VCE2. with respect to triggering signal.
Result:-
An Astable Multivibrator is designed, the waveforms are observed and verified the results theoretically.
Viva questions
1. What are the other names of Astable multivibrator?
2. The smaller allowable interval between two triggers is called the __ of the flip-flop.
3. Explain charging and discharging of capacitors in an Astable Multivibrator?
4. How can an Astable multivibrator be used as VCO?
5. What are symmetrical triggering and unsymmetrical triggering?
6. What are the applications of Astable Multivibrator?
7. Which multivibrator has two quasi-stable states? What is duty cycle?
8. What is the formula for frequency of oscillations?
9. An astable multivibrator is used as a ___ generator.
10. Design R and C for a frequency of 2KHz of a symmetric Astable oscillator.
Design problems
1. Design a collector coupled astable multivibrator using 2-BC107 transistors to operate at 1.5KHz and with a duty
cycle of 45% hfe min)=40, VCC=12V, IC(sat)=10mA.
2. Design voltage to frequency converter using astable multivibrator.
Outcomes: After finishing this experiment students are able to design Astable Multivibrator and explain the
operation of the same.

29
Experiment: 7
MONOSTABLE MULTIVIBRATOR
Aim:-
To design a monostable multivibrator for the Pulse width of 0.03mSec. Choose ICmax = 15mA, VCC = 12V,
VBB = 15V, R1 = 10K and take the margin of –1.18V to keep the OFF Transistor in OFF state when no trigger is
applied.
Pre Lab:-
1. Study the working of mono stable multivibrator.
2. Study the different triggering methods.
3. Study the data sheet.
Objectives:
1. To study the operation and observe the wave forms of Monostable Multivibrator.
2. To Design a Monostable multivibrator for the pulse width of 0.3mSec.
Apparatus:-
1. Monostable Multivibrator trainer kit
3. CRO
4. Multi-meter
5. Connecting patch cards
Circuit Diagram:-
Theory:
The monostable circuit has one permanently stable and one quasi-stable state. In the monostable configuration, a
triggering signal is required to induce a transition from the stable state to the quasi- stable state. The circuit remains in
its quasi-stable for a time equal to RC time constant of the circuit. It returns from the quasi-stable state to its stable

30
state without any external triggering pulse. It is also called as one-shot, a single cycle, a single step circuit or a
univibrator.
Operation:
Assume initially transistor Q2 is in saturation as it gets base bias from VCC through R. coupling from Q2 collector to Q1
base ensures that Q1 is in cutoff. If an appropriate negative trigger pulse applied at collector of Q1 (VC1) induces a
transition in Q2, then Q2 goes to cutoff. The output at Q2 goes high. This high output when coupled to Q1 base, turns it
ON. The Q1 collector voltage falls by IC1 RC1 and Q2 base voltage falls by the same amount, as voltage across a
capacitor ‘C’ cannot change instantaneously.
The moment, a negative trigger is applied at VC1, Q2 goes to cutoff and Q1 starts conducting. There is a path for
capacitor C to charge from VCC through R and the conducting transistor Q1. The polarity should be such that Q2 base
potential rises. The moment, it exceeds Q2 base cut-in voltage, it turns ON Q2 which due to coupling through R1 from
collector of Q2 to base of Q1, turns Q1 OFF. Now we are back to the original state i.e. Q2 is ON and Q1 is OFF.
Whenever trigger the circuit into the other state, it cannot stay there permanently and it returns back after a time period
decided by R and C.
Pulse width is given as T = 0.69RCsec.F
Design :-
T =  ln 2
T = 0.69 RC
Choose C = 10nf
T = 0.69 x68k x 10 x 10-9
= 0.46ms
RC =
maxC
CESatCC
I
VV 
RC = (12 – 0.2) / 15mA  1K
Minimum requirement of for more margin, given
| VB1|  0.1 VB1 = -1.185
VB1 =
21
2
21
1
RR
RV
RR
RV CESatBB




-1.18 =
21
21 2.012
RR
RR


; given R1 = 10K
R2 = 100KΩ
Procedure:-
1. Switch ON the trainer kit and observe power indication.
2. Wire the circuit as shown in the circuit diagram.
3. Calculate the pulse width (T) of the Monostable O/P with the selected values of R & C on the CRO. See
that CRO is in DC mode.
4. Select the triggering pulse such that the frequency is less than 1/T
5. Apply the triggering input to the circuit and to the CRO’s channel 1 to trigger the beam. Apply
Monostable O/P to the Channel 2 of the CRO.
6. Adjust the triggering pulse frequency to get stable pulse on the CRO and now measure the pulse width
and verify with the theoretical value.
7. Obtain waveforms at different points like VB1, VB2, VC1 & VC2.

31
8. Repeat the experiment for different combinations of R & C ( C = 1nf, 100nf). Calculate R for same value
of T = 0.3 mSec.
EXPECTED WAVE FORMS:
Post-Lab:-
1. Draw the waveform for VBE , VBE2 ,VCE & VCE2. with respect to triggering signal
Result:-
A collector coupled Monostable Multivibrator is designed, the waveforms are observed and verified the
results theoretically.
Viva Questions:
1. What is a multivibrator? What is a quasi state?
2. What are applications of Monostable Multivibrator?
3. The monostable multivibrator is also called __, ___, __, ___ or ___.
4. A Monostable Multivibrator generates __ waveform.
5. Why is the time period T also called Delay time?
6. Justify, Why Monostable Multivibrator is called one-shot circuit?
7. In monostable multivibrator, the coupling elements are __.
8. What is the formula for the pulse width of a Monostable multivibrator? To get a pulse width of 2 mSec., get the
values of R and C.
9. ___ triggering is used in monostable multivibrator.
10. What is monostable multivibrator and define its working states.
Design Projects
1. Design a collector coupled monostable multivibrator using 2-BC107 transistor with 5ms quasi stable state duration
VCC=10V , hfe(min)=30 IC(sat)=5mA.
2. Verify the output of monostable multivibrator by using different triggering methods.
Outcomes: After finishing this experiment students are able to design Monostable Multivibrator and able to explain
its operation.

32
Experiment: 8
SCHMITT TRIGGER
Aim:-
(a) To design the circuit of Schmitt trigger with UTP = 3V, LTP = 1.5V ,Vcc = 15V ,Rs = 1k,Rc2 = 3k,R1 = 15k R2
= 4.7k
(b) To Obtain the UTP and LTP values practically and verify with theoretically
(c) To obtain square wave from the sine wave.
Pre lab:-
1. Study the working of Schmitt trigger.
2. Study the data sheet of B C 107.
Objectives:
1. To design the circuit of Schmitt trigger with UTP=2.2V and LTP=1V.
2. To obtain square wave from sine wave.
3. To obtain UTP and LTP values practically
Apparatus:-
(1) Function Generator
(2) Multimeter
(3) C.R.O
(4) Connecting patch chords.
Circuit Diagram:-
Theory:
In digital circuits fast waveforms are required i.e, the circuit remain in the active region for a very short time
(of the order of nano seconds) to eliminate the effects of noise or undesired parasitic oscillations causing
malfunctions of the circuit. Also if the rise time of the input waveform is long, it requires a large coupling
capacitor. Therefore circuits which can convert a slow changing waveform (long rise time) in to a fast
changing waveform (small rise time) are required. The circuit which performs this operation is known as
“Schmitt Trigger”.
In Schmitt trigger circuit, the output is in one of the two levels namely low or high. When the input voltage
is raising above the UTP (upper threshold point) i.e. V1, the output changes to high level. Similarly when a
falling output voltage passes through a voltage V2 known as lower threshold point (LTP), the output

33
changes to low. The level of the output changes V1 is always greater than V2.The differences of these two
voltages is known as “Hysteresis”.
Procedure:-
(1) Switch ON the trainer
(2) Connect the circuit as shown in Fig.
(3) With Vi = 0V, measure the output voltage.
(4) Slowly increase the input voltage from 0V to maximum and observe the output for the transition.
(5) Obtain the voltage at which the LOW to HIGH transition is occurred and i.e., the UTP and now measure the
output voltage.
(6) Now, slowly decrease the input voltage and observe for the HIGH to LOW transition at the output, the input
voltage at this point is called the LTP.
(7) Apply a sine wave input to the circuit
(8) Observe the input and output waveforms on CRO.
(9) Vary the input frequency and comment on the results obtained.
(10) Repeat the experiment with RE2.
(11) Verify the result theoretically.
Observations:
With Re = 480ohms
D C A C
UTP = 2.9V UTP = 3V
LTP = 1.8V LTP = 2V
VH = UTP – LTP VH = UTP – LTP
Theoretical Calculations:-
V1 calculation:
VBE2 = 0.6V for Si
Vr1 = 0.5V
(=VBE at cut in)
V’ =
211
2
RRR
RV
C
CC

; Rb =
211
112 )(
RRR
RRR
C
C


VCC = 12V
VEN = (V’ - VBE2) *
)1(
)1(


FEeb
FEe
hRR
hR
(accurate value) V1 = V’ = 0.1 v (approximate value)
V2 calculation:
a =
21
2
RR
R

; R =
211
211 )(
RRR
RRR
C
C


;
Re’ = Re(1+
FEh
1
);
VBE = 0.6V
Vr = 0.5V
(or) V2 = VBE1 +
ReaR
Re
(V’ – Vr2) (approximately)
Expected Waveforms:-
V1 = VEN + Vr1
V2 = VBE1 +
'
/'
eR
FEse
Ra
hRR


(V’ - Vr2)

34
Post lab:-
1. Draw the output waveform with respect to input wave form.
2. Indicate the UTP & LTP.
3. Draw the hysterisis curve.
Result:-
Viva Questions:
1. What is Schmitt Trigger?
2. What are the applications of Schmitt Trigger?
3. Define hysteresis action?
4. Why Schmitt Trigger is called a squaring circuit?
5. Define UTP? Write its expression.
6. Define LTP? Write its expression.
7. What is the difference between a Binary and Schmitt Trigger?
8. How noise can be eliminated on a given signal using Schmitt Trigger?
9. Explain how a Schmitt Trigger converts a sine wave to a square wave?
10. A Schmitt trigger exhibits hysteresis when loop gain is ___.
Design Projects
1. Design Schmitt trigger circuit to get UTP=5V and LTP=7V for VCC=15V.
. Outcomes: After finishing this experiment students are able to Design Schmitt trigger circuit using transistor and
they are able to find UTP and LTP.

35
Experiment: 9
UJT RELAXATION OSCILLATOR
Aim:
To verify the astable operation by using UJT.
Pre Lab:-
1. Study the working of UJT as a relaxation oscillator.
2. Study the data sheet of 2N 2626 UJT.
Objective:
1.To Study the operation of UJT as a Relaxation Oscillator
2.Calculate sweep time and flyback time of UJT relaxation oscillator.
Apparatus:-
1) Bread Board
2) Capacitor- 0.1μF
3) Resistors – 33kΩ - 1No, 560Ω - 1No, 1kΩ - 1No
4) CRO
5) CRO connecting probes
6) DC Power Supply
7) UJT – 2N2646
Procedure:-
1) Connect the circuit as per circuit diagram
2) Observe the wave – form
a. Across the capacitor
b. AT B1 terminal of UJT
c. At B2 terminal of UJT.
Circuit Diagram:-
Circuit Diagram:-
Theory:

36
Pin assignment of UJT:
Viewing from the side of pins
The uni-junction transistor (UJT) has two doped regions with three external leads. It has one emitter and two bases.
The emitter is heavily doped having many holes. The n-region is lightly doped. For this reason, the resistance between
the bases is relatively high, typically 5KΩ to 10 KΩ when the emitter is open. This is called Inter-base Resistance RBB.
Operation:
The inter-base resistance between B2 and B1 of the silicon bar is, RBB=RB1+ RB2.
With emitter terminal open, if voltage VBB is applied between the two bases, a voltage gradient is established along the
n-type bar.
The voltage drop across RB1 is given by = ηVBB, where the intrinsic stand-off ratio
η =RB1/( RB1 + RB2)
The typical value of η ranges from 0.56 to 0.75.
This voltage V1 reverse biases the PN-junction and emitter current is cut-off. But a small leakage current flows from
B2 to emitter due to minority carriers.
The equivalent circuit of UJT is shown in figure below.
Calculations: -
T1 = RC In
PBB
VBB
VV
VV


T2 = Rb1 C In
V
P
V
V
Observation Table:
X Theoretical Practical
T1

37
Model Graph
Post Lab:-
1. Draw the waveform for trigger input at base 2 of the UJT & the
Out put sweep voltage wave form at emitter E.
Result:-
Hence the astable operation by using UJT is verified.
Viva Questions:
1. What is a relaxation oscillator?
2. The most useful applications of a relaxation oscillator waveform are _, _
3. What is meant by intrinsic stand off ratio of an UJT?
4. Why UJT is called as negative resistance device? When the negative resistance exists in UJT characteristics.
5. Draw the equivalent circuit of an UJT.
6. The deviation from linearity of a relaxation oscillator is expressed in three ways. What are they?
7. The other names of Relaxation oscillator are _, _ & _.
8. The time during which the output increases linearly is called the __ and the time required by the sweep voltage to return to the
initial value is called the __
9. When __ of a relaxation oscillator output is zero, a saw-tooth or ramp output waveform is obtained.
10. What are Peak point and valley point for an UJT? Write formula for Peak voltage.
Design problems
1. Design UJT relaxation oscillator with sweep amplitude of 6V, with sweep interval of 3ms neglect flyback time and es=0.75.
2. Design UJT relaxation oscillator with sweep amplitude of 10V, with sweep interval of 2ms neglect flyback time and es=0.8.
Outcomes: After finishing this experiment students are able to understand the operation of UJT as a
relaxation oscillator.

38
Experiment: 10
BOOT STRAP SWEEP CIRCUIT
Aim:-
To observe and measure sweep speed of a boot – strap sweep generator.
Pre Lab:-
1. Study the working of Bootstrap Sweep Circuit
2. Study the data sheet of SL100.
Objectives:
1. To design a Boot-strap Sweep Circuit.
2. To obtain a sweep wave form.
Apparatus:-
1) Bread Board
2) Diode – 1N4007 – 1No
3) Transistor – SL 100 – 2No’s
4) Resistor – 100kΩ – 1No
10 kΩ – 2 No’s
5) Capacitor - 100μF / 25V – 1No
6) Decode Capacitance box
7) DC power supply
8) Function Generator
9) CRO
10) CRO Connecting probes
Theory:-
The input to the transistor ‘Q1’ is the gating waveform from a multivibrator like a square wave under
quiescent conditions, i.e before the application of the gating waveform at t = 0, Q1 is in saturation because it gets
enough base drive from Vcc through RB. So the voltage across the capacitor which is also the voltage at the collector of
Q1 is in saturation because it gets enough base drive from VCC through RB. So the voltage across the capacitor which is
also the voltage at the collector of Q1 and the base of Q2 which VCE (sat). Since Q2 is conducting and acting as an
emitter follower, the voltage at emitter of Q2 which is also the o/p voltage is less than this base voltage by VBE2 i.e.
V0 = VCE (sat) – VBE2
Is a small negative voltage if we neglect this small voltage as well as the small drop across the diode D, Then the
voltage across C1 as well as across ‘R’ is Vcc. Hence the current IR through ‘R’ is VCC / R. since the quiescent o/p
voltage at the emitter Q2 is close to zero, the emitter current of ‘Q2’ is VEE / RE. Hence the base current of Q2 is IBZ =
VEE / hfe RE.
iR = iC1 + iB2
Since the base current of ‘Q2’ i.e iB2 is very small compared to the collector current iC1 of Q1; iC1 = IR =
R
VCC

39
Circuit Diagram:-
Procedure:-
1) Connect the circuit as shown in the figure
2) Apply a square wave of 10Vp-p and 1KHZ
3) Connect the CRO at the o/p of ‘Q2’ transistor
4) Observe the o/p waveform on the CRO by varying decade capacitance value
5) Calculate the sweep speed theoretically and practically.
Calculations: -
Sweep amplitude Vs(max) =
RC
TV gCC .
Rise time (Ts) = RC
Retrace time ( Tr) =












RRb
hfe
VCV CCs
1
/
; hfe = 268
Sweep speed =
RC
VCC

40
EXPECTED WAVEFORMS :
Conclusion:
Conclusions can be made on sweep time Ts and retrace time TR and sweep voltage Vs of the sweep waveform
theoretically and practically and also made on if the output waveform of the Bootstrap are identical with the
theoretical wave forms or not.
Post Lab:-
1. Draw the waveform for VB1, IC1 and VO.
2. Calculate Sweep time(TS) and Restoration time(TR).
Result:-
Hence the boot – strap sweep generator circuit is observed and studied
VIVA QUESTIONS:
1. Define a Voltage time base generator, a current time base generator and a linear time base generator.
2. What is the relation between the slope error, displacement error and transmission error?
3. What are the various methods of generating time base wave-form?
4. Which amplifier is used in Boot-strap time base generator?
5. Which type of sweep does a bootstrap time-base generator produce?
6. What is the gain of the amplifier used in Bootstrap time base generator?
7. What is retrace time? Write the formula for the same for Bootstrap time base generator.
8. What is the formula for sweep amplitude in Bootstrap time base generator?
9. To have less flatness time of sweep signal, then the gate signal time has to be __.
10. A Bootstrap sweep circuit employs __ type of feedback.
Design problem:
1. Design Boot-strap Sweep Circuit with sweep amplitude of 8V, with sweep interval of 1ms neglect flyback time and es=0.25.
2. Design Boot-strap Sweep Circuit with sweep amplitude of 15V, with sweep interval of 2ms neglect flyback time and es=0.1.

41
Experiment: 15
REALIZATION OF LOGIC GATES
AIM : To study the various logic gates by using discrete components.
Component Required :
1. Resistors - 1k -1, 10 k -2
2. IN4007 Diodes – 2 no
3. Transistor 2N2369
Apparatus Required:
1. Power supply 0-30V
2. Bread board
3. Connecting wires
4. Multimeter
THEORY:
AND GATE:
The AND gate as a high output when all the inputs are high the figure 1 shows one way to
build the AND gate by using diodes.
Case 1: When both A and B are low then the diodes are in the saturation region then the supply from VCC will
flow to the diodes then the output is low.
Case 2: When A is low and B is high then diode D1 will be in the saturation region and D2 will be in the Cut-

42
off region, then the supply from VCC will flow through diode D1 then the output will be low.
Case 3: When A is high, B is low the diode D1 will be in the Cut-off region and diode D2 will be in saturation
region then the supply from VCC will flow through the diode D2, therefore the output will be low.
Case 4: When both the A and B are high then the two diodes will be in Cut-off region therefore the supply from
VCC will flow through Vout then Vout is high.
An OR gate has two or more inputs but only one output signal. It is called OR gate because the
output voltage is high if any or all the inputs are high.
The figure 2 shows one way to build OR gate (two inputs) by using diodes.
Case 1: When A and B are low then the two diodes D1 and D2 are in Cut-off region. Then the Vout is low.
Case 2: When A is low and B is high then the diode D1 is in Cut-off region and diode D2 is in saturation
region, then the Vout is high.
Case 3: When A is high and B is low then the diode D2 is in saturation region and diode D1 is in Cut-off
region, then the Vout is high.
Case 4: When both A and B are high the diodes D1 and D2 are in saturation region then the
output Vout is high.

43
NAND gate is referred to as NOT AND GATE because the output is Y  A.B read this as Y = NOT A AND B
or Y = Compliment of A AND B. By this gate the output is low when all the inputs are high.
The Inverter or NOT gate is with only one input and only one output. It is called inverter because the

44
output is always opposite to the input.
The figure5 shows the one way to build inverter circuit by using transistor (CE mode) when the Vin is
low then the transistor will be in the Cut-off region. Then the supply from VCC will flow to Vout. Then the Vout
is high. When Vin is high then the transistor is in the saturation region then the supply from VCC will flow
through the transistor to the ground, then the Vout is low.

45
PROCEDURE:
1. Connect the circuit as shown in figure 1
2. Apply ‘0v’to logic ‘0’and 5V to logic ‘1’using power supply.
3. Verify the truth tables of various gates for different conditions of inputs.
4. Repeat the steps 1&2 for figures 2, 3, 4 & 5.

46
TRUTH TABLES

47
Experiment: 11
Miller Sweep Circuit
Aim:-
To observe and measure sweep speed of a Miller sweep generator.
Pre Lab:-
1. Study the working of Miller Sweep Circuit
2. Study the data sheet of SL100.
Apparatus:-
1) Bread Board
2) Transistor – SL 100 – 2No’s
3) Resistor R = RC = 10kΩ – 1No
Rb=22 kΩ – 1 No
Ra = 1KΩ- 1No
4) Capacitor – Cc = 0.1μF – 1No
C = 0.01μF – 1No
5) DC power supply
6) Function Generator
7) CRO
8) CRO Connecting probes
Theory:-
The miller sweep circuit or miller integrator generator is a precise and linear ramp voltage using active devices
providing required feedback, the effective time constant and supply voltage is enhanced. Miller sweep circuit is the
basic schematic of a widely used sawtooth generator. The amplifier acts to increase the aiming potential; thus,
linearity is improved and the output amplitude is increased. As the integral of a step function is a ramp, it is evident
that this circuit would provide a sawtooth output as shown in figure 2,however we will observe not exactly same
wavform but close one in the experiments
The output of the miller sweep circuit is a negative going ramp.The transistor Q1 is biased such that it is ON in the absence of an
input signal. So the potential at its collector is Vce saturation.The collector voltage of the transistor Q2 is Vcc since it is in off
state. The capacitor C is charged to Vcc through Rc and Q1.
When the negative going input pulse turns Q1 off collector potential of Q1 rises and in turn ,makes Q2 On.The sudden rise of the
voltage at the left side of the capacitor immediately transmit the right side creating an overshoot in the output. Then the capacitor

48
discharges through Q2 and R.For linear charging of the capacitor , design criteria is Ts=RC where Ts is the time period of falling
sweep.
Circuit Diagram:-
Otput Waveforms

49
Calculations:-
When Q1 is in sat and Q2 is in cut-off and the voltage over the capacitor C is charged to vcc through Rc.
The time constant τR = Rc *C
When Q1 is in cut-off and Q2 is Active and the time constant of the circuit is τs = RTh where RTh is thevenin
equivalent resistance between terminal a and b
RTh = (1+β) Rc τs = (1+β) Rc *C
Ts is called as the sweep time and Ts = τs, TR is called as the recovery time and TR = 5τR * TR can be reduced by
decreasing the value of RC,,but this degrades the linearity of the sweep
Post Lab:-
1. Draw the waveform for Vce sat.
2. Calculate Sweep time(TS) and Restoration time(TR).
Result:-
Hence the miller – sweep generator circuit is observed and studied

50
Experiment: 10
SAMPLING GATES
AIM: To observe the output of a bidirectional sampling gate for given input of a sine wave with a gating
signal of square wave.
APPRATUS REQUIRED:
S.No
Name of the component/
equipment
Quantity
1 Transistor (BC 107) 1
2 Resistors, 220KΩ
5.6 KΩ
2
1
3 CRO 1
4 Function generator (1MHz) 2
5 Regulated power supply 1
CIRCUIT DIAGRAM:
THEORY:

51
Sampling gate is a transmission network which transmits input wave from in a particular interval of time
only, and for remaining time output is zero. There are two types of sampling gates. 1. Unidirectional
sampling gates, 2. Bidirectional sampling gates, unidirectional sampling gates are those which
transmit signals of only one polarity. Bidirectional sampling gates are those which transmit signals of both
polarities when getting signal is at it’s lower level transmitter is well cut off and output is Vcc. When gating
signal is at its higher level transistor goes in to active region so input signal is sampled and appears at
output.
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Generate a control voltage Vc of 4V peak to peak, frequency 1KHz, and apply it to the circuit.
3. Apply the input signal with a small peak to peak voltage.
4. Observe the output wave forms and Vc simultaneously and note down the parameters of waveforms.
5. Plot the graph between Vs, Vc and output waveform with respect to time.
MODEL WAVE FORMS:
RECORD OF OBSERVATIONS:

52
V Output =
Time period =
PRECAUTIONS:
1. Connections must be done carefully.
2. Observe the output waveforms without parallel error.
RESULT:
The performance of the sampling gates is observed.
QUESTION & ANSWERS:
1. What are the other names of the sampling gates?
Ans. Linear gate, transmission gate.
2. What do you meant by pedestal?
Ans. Pedestal is the base voltage in the output on which the input signal is superimposed.
3. What are the applications of sampling gates?
Ans. Multiplexers, sample & hold circuit, digital to analog converter.

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