3. 3
Conceptual view of ATPG
Generate an input test vector that can distinguish the defect free
circuit from the hypothetically defective one
4. 4
Boolean difference method
Theoretical basis – Boolean difference
The output of the circuit is given as 𝑓 = 𝑥. 𝑦 + 𝑦 . z
Let target fault be y s-a-0 . Under this condition, the output of the
faulty circuit is shown to be 𝑓𝑦 = f/ y = 0
Generate an input test vector such that 𝑓𝑦 ⊕ 𝑓𝑦 = 1
5. 5
Boolean difference method
𝑓𝑦 ⊕ 𝑓𝑦 = 1 if and only if 𝑓𝑦 and 𝑓𝑦 result in opposing logic
values
Any TV that can set 𝑓𝑦 XOR 𝑓𝑦 = 1 is able to produce opposing
values at the outputs of the fault-free and faulty circuits
respectively
𝑑𝑓
𝑑𝑦
= 𝑓𝑦 ⊕ 𝑓𝑦
Now to test the fault say y at s-a-0, we need to initialize the
node y to 1 (i.e., y = 1) and
𝑑𝑓
𝑑𝑦
= 1 i.e., y .
𝒅𝒇
𝒅𝒚
= 1
Similarly, to test the fault say y at s-a-1 i.e., 𝒚 .
𝒅𝒇
𝒅𝒚
= 1
6. 6
Boolean difference example
Find TV to test fault s-a-0 at node y using Boolean difference method
y .
𝐝𝐟
𝐝𝐲
= y. 𝐟 𝐲 ⊕ 𝐟 𝐲 = y. 𝐱 ⊕ 𝐳 = 𝐱 . y . z + x. y. 𝐳
y .
𝐝𝐟
𝐝𝐲
= 1 will give the required TV
TV will be x y z = {011, 110}
𝑓 = 𝑥. 𝑦 + 𝑦 . z ; 𝑓𝑦 = 𝑥 ; 𝑓𝑦 = 𝑧
7. 7
Boolean difference example
Find TV to test fault s-a-0 at node w using BD method
w .
𝐝𝐟
𝐝𝐰
= w. 𝐟 𝐰 ⊕ 𝐟 𝐰 = 𝐲 . z 𝟏 ⊕ 𝐱. 𝐲 = 𝐲 . z 𝐱 + 𝐲 = 𝐱 𝐲 𝐳 + 𝐲 z =𝐲 z
w .
𝐝𝐟
𝐝𝐰
= 1 will give the required TV
TV will be x y z = {x01}
𝑓 = 𝑥. 𝑦 + 𝑤 ; 𝑤 = 𝑦 . z ; 𝑓𝑤= 1 ; 𝑓𝑤 = 𝑥. 𝑦
8. 8
Boolean difference example
Find TV to test fault s-a-0 at node Z using BD method
z .
𝑑𝑓
𝑑𝑧
= z. 𝑓𝑧 ⊕ 𝑓𝑧 = 1 will give the required TV
But, 𝑓𝑧⊕𝑓𝑧 = 0
The condition for testability ( 𝑓𝑧⊕𝑓𝑧 = 1 ) is not satisfiable
Hence, the fault is undetectable
Redundancy in the circuit is the cause for undetectable faults
𝑓 = 𝑥. 𝑦 + 𝑥. 𝑦. 𝑧 ; 𝑓𝑧= 𝑥. 𝑦 ; 𝑓𝑧 = 𝑥. 𝑦
9. 9
Boolean difference method
Summary
Given a circuit with output f and fault α s-a- b
The set of test vectors that can detect this fault
includes all the vectors that satisfy
(α = 𝑏 ).
𝑑𝑓
𝑑α
= 1