The document describes a technique for timing-driven variation-aware nonuniform clock mesh synthesis. The technique involves four main stages: 1) deriving a timing constraint graph from static timing analysis, 2) generating a skew map of rectangular regions with different skew requirements, 3) removing overlapping rectangles to generate non-overlapping polygons, and 4) generating a clock mesh for each polygon where mesh density satisfies skew variations. The technique aims to generate a clock mesh that satisfies maximum skew variation requirements while considering process, voltage, and temperature variations.