2. OutlinesOutlines
• Introduction
• SOI Technologies
• Advantages Of SOI
• SOI Devices
• Applications
• Conclusion
• References
JNU ECE CA12014 SOI TECH 2
3. IntroductionIntroduction
• Increasing demand of high performance, low
power, small area can be achieved by SOI Tech.
• SIO2 layer is created by flowing oxygen onto silicon
wafer.
• Insulating layer reduces junction capacitance and
also reduce power consumption.
• Floating body
• Less area because no metal contact to wells
JNU ECE CA12014 SOI TECH 3
5. Partially Depleted vs. Fully-DepletedPartially Depleted vs. Fully-Depleted
• Partially-depleted SOI
o The body is thicker than the depletion region, so bulk
voltage can vary depending on the amount of charge
present
o This varying charge changes Vt because of the body
effect
• Fully-depleted SOI
o Body is thin, depletion region spans bulk
o Body charge is fixed, body voltage does not change
o Harder to make because of thin body
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6. SOI TECNOLOGIESSOI TECNOLOGIES
• SOS (Silicon-On-Sapphire)
• SIMOX (Separation by IMplanted OXygen)
• BESOI (Bond and Etch-back SOI)
• Smart- Cut®
• ELTRAN® (Epitaxial Layer TRANsfer)
6JNU ECE CA12014 SOI TECH
14. Benefits of SOIBenefits of SOI
• Simple Isolation
• Higher Density
• Reduced S/D junction capacitance
• No latch up
• Low soft Errors
• Speed Increases
• Less Power consumsion
• Less area
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15. JNU ECE CA12014 SOI TECH 15
Fully depleted SOI
FD-SOI
Implementation
ARM7
SOI provides a viable low-power solution
1/3 power consumption
of bulk device with
same performance
16. JNU ECE CA12014 SOI TECH 16
The inherent advantages of SOI are essential today
• Compared to bulk-CMOS, SOI technology offers
–
–
–
–
–
Lower power, 30- 40% lower power (or higher
performance)
Less process complexity and variability
More reliable: 10x soft error rate reduction and no
latch up
FD- SOI/ FinFET: stable SRAMs
Simplifies Digital, Analog and RF integration in SoCs
17. SOI DisadvantagesSOI Disadvantages
• Floating body causes the History Effect
o This changes Vt, which changes the delay of the circuit
• Self-heating
• Modeling issues
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18. Commercialized SOI WafersCommercialized SOI Wafers
• SOS : Kyocera, Union Carbide, Asahi kasei
• SIMOX : IBIS(Mitsubishi)
: NSC, Komatsu(NTT)
• Bond and layer transfer SOI
• :SOITEC,Canon,SiGen
• BESOI : Isonics, BCO, Hughes, SiBond
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19. Present SOI Device and CircuitsPresent SOI Device and Circuits
• IBM : CPU with 300mm, 0.1 micron, Cu
• Motorola : commercial G4, 2GHz G5 power PC
• Intel : DST- sub 30nm TSOI, sub 70nm gate
• AMD :mobile,space,64bitMPU
• Honeywell : Rad-hard, space application
• HP : 64-bit RISC processor with copper
• IBM, Toshiba, Sony : supercomputer-on-chip
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20. Present SOI Device and Circuits 2Present SOI Device and Circuits 2
•Hitachi : mainframe computers
•Mitsubishi : RF/anlog devices
•Epson : low-voltage ASICs
•Fujitsu : high-speed logic devices (adder circuit)
•Seiko, Casio : wrist watch chip
•Oki : low power high speed rf devices
•TSMC : 90 nm MOSFET with SOI
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21. ApplicationsApplications
• Low power, high speed IC
• ULSI Circuit
• Rad-hard IC
• High power device
• High temperature device
• Si MMIC
• Sensor & MEMS application
JNU ECE CA12014 SOI TECH 21
22. I
(In
SOI is part of your daily life!
Computing
Gaming
VN
Vehicle Networking)
Automotive
Quad-Core
DSP MSC8144
Networking
Images, Ultra LP
22JNU ECE CA12014 SOI TECH
23. Tilted 3-D cross section
of a FinFET on SOI
Emerging
SOI application:
FinFETs manufacturing low
variability & low cost
Challenge: In bulk-CMOS it’s
difficult to achieve an exact fin-height
and minimize this additional variability.
Film
Thickness
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24. Emerging
SOI application:
Optical waveguides
Challenge: To minimize signal
loss and cost for optical interconnects
both noise isolation and precision
manufacturing are essential for highly
integrated solutions.
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25. Emerging
SOI application:
CMOS image sensor
Challenge: Less expensive
cameras and mobile phones demand
small and low-cost image sensors, without
trading off sensitivity or quantum efficiency.
Light passing through
a thinned silicon wafer
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27. JNU ECE CA12014 SOI TECH 27
SOI / XDM10 process
> 350V D-S
breakdown
Emerging
SOI application:
High-voltage switching
Challenge: Car batteries will increase to
48V, hybrid batteries
output 200 – 300V and > 100A currents.
28. JNU ECE CA12014 SOI TECH 28
26 members so far, focused on reducing power
The SOI Industry Consortium
includes leaders in the
electronics industry from users
& enablers to suppliers &
manufacturers
29. ConclusionConclusion
• After studying the various circuit issues of both the
technologies. SOI gives the superior results than Bulk
technology, which increases
• The circuit performances, high reliability, removes
the parasitic capacitance, punch through issue
and the circuit compactness.
• Hence SOI technology is the leading and
upcoming technology in both micro and nano
electronics.
JNU ECE CA12014 SOI TECH 29
30. SOI ReferencesSOI References
• Proceedings
• ECS SOI symposium proceedings
• IEEE SOI conference proceedings
• Consortium industry
• TEXT
• J.B.Kuo : CMOS VLSI Engineering : Silicon on
insulator
JNU ECE CA12014 SOI TECH 30
