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MEMBERS
 Tushar Swami
 Vikas Prasad
 Tanish Garg
 Anurag Aggarwal
OUTLINE
 What is RISC?
 CISC
 Background and History
 Characteristics
Pipelining
Hardware
 RISC v/s CISC
 Performance Equation
 Applications of RISC
 RISC & CISC Convergence
ACKNOWLEDGEMENT
We would like to express our special thanks of gratitude to our teacher
Dr. Praveen Kant Pandey who gave us the golden opportunity to present this
wonderful presentation on the topic RISC, which also helped us in doing a lot of
Research and we came to know about new things. We are really thankful to her.
WHAT
IS
RISC???
INTRODUCTION
 RISC – Reduced Instruction Set Computer
 RISC is a type of microprocessor architecture that utilizes
 a small, highly-optimized set of instructions
 rather than a more specialized set of instructions.
 The main alternative for RISC is CISC ,which stands for complex instruction set
computer.
 CISC is the older approach, that came about to maximize performance of earlier
computer’s. Where instructions were executed sequentially.
The instruction set is the
hardware language that tells the
processor what to do.
Sources : http://search400.techtarget.com/definition/RISC
BACKGROUND AND HISTORY
 RISC approach developed as a result of development in 1970’s
- increase in memory size
- decrease in cost
- advanced compilers
 In late 1970’s IBM was the first to start.
 In 1980 , David Patterson ,began the project that gives this approach RISC.
 After some years ,Stanford MIPS was developed.
Sources : http://search400.techtarget.com/definition/RISC
CHARACTERSTICS OF RISC
 Simplified instructions , taking 1 clock cycle.
 Large no. of general purpose registers.
 Circuit is much simpler.
 Fast to decode.
 Fast to execute.
 Pipelining- fetching of next instruction while
previous instruction executes.
Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/whatis/index.html
PIPELINING
Pipelining, a standard feature in RISC processors, is much like an assembly line.
A useful method of demonstrating this is the laundry analogy.
Let's say that there are four loads of dirty laundry that need
to be washed, dried, and folded.
Washer - 30 minutes
Dry - 40 minutes
Folding - 20 minutes
Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html
Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html
Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html
RISC PIPELINES
A RISC processor pipeline operates in much the same way, although the stages in the
pipeline are different
1. fetch instructions from memory
2. read registers and decode the instruction
3. execute the instruction or calculate an address
4. access an operand in data memory
5. write the result into a register
Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html
The length of the pipeline is
dependent on the length of
the longest step.
Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html
HARDARE UTILIZATION
 For any given level of general performance, a RISC chip will typically have far fewer
transistors dedicated to the core logic which originally allowed designers to increase
the size of the register set.
 RISC designs are also more likely planning to feature a
Harvard memory model, where the instruction stream
and the data stream are conceptually separated.
Sources : https://www.youtube.com/watch?v=mDrUkjOVtAU
CISC vs. RISC
CISC
 Complex Instructions.
 ADD AX,[BX + SI + 600H]
 Many operations in single
instruction.
RISC
 Simpler or reduced instructions.
 LOAD R1, addresss1
LOAD R2, address2
ADD R1, R2
STORE address1, R1
One instruction one operation.
INSTRUCTION
Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/
CISC RISC
CODE SIZE
Code size is larger but simpler.
Code size is smaller but complicated.
Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/
CISC
 Fewer register.
 These registers are designed
for special purposes.
 CISC designs provide a large
number of addressing modes.
RISC
 Large number of registers.
 Here registers are identical so
any register can be used for
any purpose.
 RISC designs have single
addressing modes.
REGISTERS AND ADDRESSING MODE
Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/
CISC
 Slower to execute.
 Difficult to decode.
 Instruction size varies in
different instructions.
 Complex circuit design.
RISC
 Faster execution.
 Easy to decode.
 Same instruction size in every
instructions.
 Circuit design is simpler.
Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/
RISC
APPLICATIONS
LOW END &
MOBILE SYSTEM
•ARM ARCHITECTURE
o Android based systems/ Apple iPhone/
Nintendo GBA etc.
•MIPS line
o in PlayStations, Nintendo 64 etc.
•Atmel AVR
o Xbox handheld controllers to BMW cars
HIGH END RISC &
SUPERCOMPUTING
•MIPS
o used in embedded system in routers, used
by Digital Equipment Corporation etc.
•IBM’S Power Architecture
o In many IBM’s supercomputers, workstations
etc.
•Alpha
o In Single-board computers, Servers &
Supercomputers from Digital Equivalent
Cooperation etc.
RISC APPLICATIONS
Sources : http://embeddedcraft.org/
ARM Architecture
• Developed by Advanced RISC
Machines (ARM).
• ARM makes 32-bit & 64-bit RISC
multi-core processors.
• Features of ARM architecture:
 A load/store architecture
 An orthogonal instruction set.
 Fixed instruction width
 Mostly single clock-cycle
execution.
 Enhanced power-saving design.
 Hardware virtualization supports.
ARM BASED PRODUCTS.
Sources : http://embeddedcraft.org/
http://whatis.techtarget.com/definition/ARM-processor
MIPS
• It includes MIPS I, MIPS II, MIPS III,
MIPS IV, MIPS V, MIPS32, and
MIPS64.
• Key concepts:
• five-stage execution pipeline
• regular instruction set, all
instructions are 32-bit
• no status register or instruction side-
effects
• no complex instructions.
• only the load and store instruction
access memory.
• optional coprocessors for system
management and floating-point
• flat address space of 2^32 bytes of
main memory
MIPS- Microprocessor without
Interlocked Pipeline Stages
Sources : http://embeddedcraft.org/
https://tams.informatik.unihamburg.de/applets/webdemos/mips.html
DISCUSSION
PERFORMANCE EQUATION
The CISC approach attempts
to minimize the number of
instructions per program,
sacrificing the number of
cycles per instruction.
RISC does the opposite,
reducing the cycles per
instruction at the cost of the
number of instructions per
program.
Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/index.html
RISC & CISC CONVERGENCE
With time and developments, it was observed that the line of distinction between two
hardware began to blur.
In fact two hardware seem to have adopted the strategies of the other.
 CISC - now executes more than one instruction within a single clock.
 This also allows CISC chips to make use of pipelining.
 With other technological improvements, it is now possible to fit
many more transistors on a single chip.
 RISC - incorporate more complicated, CISC-like commands.
Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/developments/index.html
CONCLUSION
 Experts’ talk - we are in a "post-RISC" era, in which the two styles have become so
similar that distinguishing between them is no longer relevant.
 RISC chips still retain some important traits.
- utilize uniform, single-cycle instructions.
- register-to-register, load/store architecture.
- still have a large number of general purpose registers.
Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/developments/index.html
RISC - Reduced Instruction Set Computing

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RISC - Reduced Instruction Set Computing

  • 1.
  • 2. MEMBERS  Tushar Swami  Vikas Prasad  Tanish Garg  Anurag Aggarwal
  • 3. OUTLINE  What is RISC?  CISC  Background and History  Characteristics Pipelining Hardware  RISC v/s CISC  Performance Equation  Applications of RISC  RISC & CISC Convergence
  • 4. ACKNOWLEDGEMENT We would like to express our special thanks of gratitude to our teacher Dr. Praveen Kant Pandey who gave us the golden opportunity to present this wonderful presentation on the topic RISC, which also helped us in doing a lot of Research and we came to know about new things. We are really thankful to her.
  • 6. INTRODUCTION  RISC – Reduced Instruction Set Computer  RISC is a type of microprocessor architecture that utilizes  a small, highly-optimized set of instructions  rather than a more specialized set of instructions.  The main alternative for RISC is CISC ,which stands for complex instruction set computer.  CISC is the older approach, that came about to maximize performance of earlier computer’s. Where instructions were executed sequentially. The instruction set is the hardware language that tells the processor what to do. Sources : http://search400.techtarget.com/definition/RISC
  • 7. BACKGROUND AND HISTORY  RISC approach developed as a result of development in 1970’s - increase in memory size - decrease in cost - advanced compilers  In late 1970’s IBM was the first to start.  In 1980 , David Patterson ,began the project that gives this approach RISC.  After some years ,Stanford MIPS was developed. Sources : http://search400.techtarget.com/definition/RISC
  • 8. CHARACTERSTICS OF RISC  Simplified instructions , taking 1 clock cycle.  Large no. of general purpose registers.  Circuit is much simpler.  Fast to decode.  Fast to execute.  Pipelining- fetching of next instruction while previous instruction executes. Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/whatis/index.html
  • 9. PIPELINING Pipelining, a standard feature in RISC processors, is much like an assembly line. A useful method of demonstrating this is the laundry analogy. Let's say that there are four loads of dirty laundry that need to be washed, dried, and folded. Washer - 30 minutes Dry - 40 minutes Folding - 20 minutes Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html
  • 12. RISC PIPELINES A RISC processor pipeline operates in much the same way, although the stages in the pipeline are different 1. fetch instructions from memory 2. read registers and decode the instruction 3. execute the instruction or calculate an address 4. access an operand in data memory 5. write the result into a register Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html
  • 13. The length of the pipeline is dependent on the length of the longest step. Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html
  • 14. HARDARE UTILIZATION  For any given level of general performance, a RISC chip will typically have far fewer transistors dedicated to the core logic which originally allowed designers to increase the size of the register set.  RISC designs are also more likely planning to feature a Harvard memory model, where the instruction stream and the data stream are conceptually separated. Sources : https://www.youtube.com/watch?v=mDrUkjOVtAU
  • 16. CISC  Complex Instructions.  ADD AX,[BX + SI + 600H]  Many operations in single instruction. RISC  Simpler or reduced instructions.  LOAD R1, addresss1 LOAD R2, address2 ADD R1, R2 STORE address1, R1 One instruction one operation. INSTRUCTION Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/
  • 17. CISC RISC CODE SIZE Code size is larger but simpler. Code size is smaller but complicated. Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/
  • 18. CISC  Fewer register.  These registers are designed for special purposes.  CISC designs provide a large number of addressing modes. RISC  Large number of registers.  Here registers are identical so any register can be used for any purpose.  RISC designs have single addressing modes. REGISTERS AND ADDRESSING MODE Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/
  • 19. CISC  Slower to execute.  Difficult to decode.  Instruction size varies in different instructions.  Complex circuit design. RISC  Faster execution.  Easy to decode.  Same instruction size in every instructions.  Circuit design is simpler. Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/
  • 21. LOW END & MOBILE SYSTEM •ARM ARCHITECTURE o Android based systems/ Apple iPhone/ Nintendo GBA etc. •MIPS line o in PlayStations, Nintendo 64 etc. •Atmel AVR o Xbox handheld controllers to BMW cars HIGH END RISC & SUPERCOMPUTING •MIPS o used in embedded system in routers, used by Digital Equipment Corporation etc. •IBM’S Power Architecture o In many IBM’s supercomputers, workstations etc. •Alpha o In Single-board computers, Servers & Supercomputers from Digital Equivalent Cooperation etc. RISC APPLICATIONS Sources : http://embeddedcraft.org/
  • 22. ARM Architecture • Developed by Advanced RISC Machines (ARM). • ARM makes 32-bit & 64-bit RISC multi-core processors. • Features of ARM architecture:  A load/store architecture  An orthogonal instruction set.  Fixed instruction width  Mostly single clock-cycle execution.  Enhanced power-saving design.  Hardware virtualization supports. ARM BASED PRODUCTS. Sources : http://embeddedcraft.org/ http://whatis.techtarget.com/definition/ARM-processor
  • 23. MIPS • It includes MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. • Key concepts: • five-stage execution pipeline • regular instruction set, all instructions are 32-bit • no status register or instruction side- effects • no complex instructions. • only the load and store instruction access memory. • optional coprocessors for system management and floating-point • flat address space of 2^32 bytes of main memory MIPS- Microprocessor without Interlocked Pipeline Stages Sources : http://embeddedcraft.org/ https://tams.informatik.unihamburg.de/applets/webdemos/mips.html
  • 25. PERFORMANCE EQUATION The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program. Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/index.html
  • 26. RISC & CISC CONVERGENCE With time and developments, it was observed that the line of distinction between two hardware began to blur. In fact two hardware seem to have adopted the strategies of the other.  CISC - now executes more than one instruction within a single clock.  This also allows CISC chips to make use of pipelining.  With other technological improvements, it is now possible to fit many more transistors on a single chip.  RISC - incorporate more complicated, CISC-like commands. Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/developments/index.html
  • 27. CONCLUSION  Experts’ talk - we are in a "post-RISC" era, in which the two styles have become so similar that distinguishing between them is no longer relevant.  RISC chips still retain some important traits. - utilize uniform, single-cycle instructions. - register-to-register, load/store architecture. - still have a large number of general purpose registers. Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/developments/index.html