ppt

1. INTERVIEW FOR Ph.D. ADMISSION FOR JULY
2023 SESSION
DESIGN OF POWER OPTIMIZED AND HIGH PERFORMANCE n x n MULTIPLIER USING QCA
1

2. INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 2
Sl.No. Degree Specialisation
University/
Institute
Year of
Passing
Marks
(%/CGPA)
1 M.E VLSI DESIGN
Akshaya College
of Engineering
andTechnology
2016 7.9(CGPA)
2 B.E ECE
Indus College of
Engineering
2012
8.2(CGPA)

3. INTERVIEW FOR Ph.D. ADMISSION FOR JANUARY 2022 SESSION 3
Sl.
No.
Designation Organisation From To
Years of
Experience
1
ASSISTANT
PROFESSOR
7214 NEHRU
INSTITUTEOF
ENGINEERINGAND
TECHNOLOGY
25.07.
2022
TILL
NOW
10MONTHS
TotalYears of Experience 10 MONTHS

4. INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 4
Sl.
No.
Title of the Paper Authors
Name of the
Journal
Year,
Volume,
Issue
Impact Factor as
per Clarivites
1
Design of Power Efficient
4x4 Multiplier Based on
Various Power Optimizing
Techniques
R Saranya,
A Venkatesh, N
Rathan
Asian Journal of
Applied Science and
Technology (AJAST)
2017/3,1,2
2
Design and Analysis of
Multi-Mode Power
Switches Based on
Various Modes in Power
Gating Architecture
R.Saranya,
S.Gladwin Moses,
N.Rathan,
M.Venkateswari
Seventh Sense
Research Group
International Journal
of Electronics and
Communication
Engineering (SSRG –
IJECE)
April 2016

5.  Multiplier is the most important building block in the design of digital circuits.
Multiplier has important role in DSP, DIP, microprocessor, and microcomputer
application.
 Among all the arithmetic operation that exist, a processor consumes most of the time
and hardware resources for carrying out multiplication when compared to other
operations like addition and subtraction.
 Compact and small circuit with low power dissipation and very small delay are main
desire of circuit designer in the field ofVLSI design
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 5

6.  The objective is to design a n x n multiplier with
low power consumption and high performance
using Quantum-dot cellular automata.
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 6

7.  The scope of the project is to provide a Multiplier circuit with low
complexity and high efficiency with power optimized and high
performance n x n multiplier using QCA.
 The proposed multiplier significantly achieves high device density,
lessened clock delay, area and cell count and also to eliminate fabrication
difficulty of crossover.
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 7

8.  NOVEL HIGH-PERFORMANCE QCA FREDKIN GATE AND DESIGNING SCALABLE QCA
BINARYTO GRAY ANDVICEVERSA
In the design of digital logic circuits, QCA technology is an excellent alternative to CMOS technology.
Its advantages over CMOS include low power consumption, fast circuit switching, and nanoscale
design. Circuits that convert data between different formats are code converters. Code converters
have an essential role in high-performance computing and signal processing.
 DESIGN OF COMPACTAND HIGH SPEED BAUGH-WOOLEY MULTIPLIER BY CSA USINGQCA
This paper utilizes the unique QCA characteristics to design a Baugh -Wooley Multiplier that is fast
and efficient to implement both signed and unsigned multiplication and comparison will be done with
present implemented multipliers. Simulation results were included using QCA. Designer and shows
that a factor of 12 smaller in terms of the area in this proposed Baugh –Wooley Multiplier design when
compared with the CMOS 32nm implementation.
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 8

9.  SYNTHESIS METHODS OF BAUGH-WOOLEY MULTIPLIER AND NON-RESTORING
DIVIDERTO ENHANCE PRIMITIVE’S RESULTS OF QCA CIRCUITS
In this paper, an accurate approach to synthesize and optimize the Baugh-Wooley multiplier
and non-restoring divider in the presence of QCA technology has been proposed.The proposed
designs are robust and utilize a wire-crossing type of single layer, with minimal clock phasing.
The synthesis approach and optimization are perfectly scalable across layout construction of
designs and can find better primitive’s results of QCA circuit performance.
 A SYSTEMATIC JOURNAL OF MULTIPLIERS ACCURACY AND PERFORMANCE
This research work outlines the most popular five multiplier techniques (likeWallace, modified,
Vedic, Russian Peasant and Logarithm) and compares them, highlights merits, demerit for
further improvements. This comprehensive study includes the systematic development,
compares the latest design of every multiplier and justified that which one is better over other
reported multiplier is also highlighted.
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 9

10.  EFFICIENT DESIGN OF QCA BASED HYBRID MULTIPLIER USING CLOCK ZONE BASED
CROSSOVER
It has been observed that the QCA cost function of the proposed multiplier better than existing
multiplier referred in the literature in terms of energy and speed. Furthermore, the proposed
multiplier significantly achieves high device density, lessened clock delay, area and cell count
and also to eliminate fabrication difficulty of crossover.
 AREA AND ENERGY OPTIMIZED MULTILAYER QCA-BASED 4N-BIT SCALABLE
MULTIPLIER (M4N-MUL)
The designs are implemented over QCA designer 2.1.0 and QCA-pro to obtain performance
cost in terms of number of cells, area, and delay and power dissipation. The present work
achieved a reduction of up to 57% in terms of area and 43% in terms of number of cells as
compared to the prior reported QCA based multiplier designs.
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 10

11.  Multiplier is the most important building block in the design of digital
circuits. Multiplier has important role in DSP, DIP, microprocessor, and
microcomputer application.
 Among all the arithmetic operation that exist, a processor consumes
most of the time and hardware resources for carrying out multiplication
when compared to other operations like addition and subtraction.
 Compact and small circuit with low power dissipation and very small
delay are main desire of circuit designer in the field ofVLSI design
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 11

12.  . A high speed and low complexity multiplier can be designed
on the basis of quantum-dot cellular automata (QCA), which
is considered promising nanotechnology.
 Quantum-dot cellular automata, is one of the most
prominent powerless nanotechnologies considered to
continue scaling-down trend of sub-micron electronics.
 It advantages small size, and better switching frequency
than traditional approaches.
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 12

13.  Rather, a columbic relation the QCA cells created paths for
propagation and the transmission of information; these
paths are called QCA wires.
 In this work we are going to design a n x n multiplier with low
power consumption and high performance using Quantum-
dot cellular automata.
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 13

14.  Novelty in research proposal is to implement the multiplier
of N bits with high device density, lessened clock delay, area
and cell count and also to eliminate fabrication difficulty of
crossover.
 The energy and speed of the multiplier will be increased.
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 14

15.  SARVARBEK ERNIYAZOV, JUN-CHEOL JEON (2019). Carry save adder and carry look
ahead adder using inverter chain based coplanar QCA full adder for low energy dissipation.
Microelectronic Engineering 211:37-43.
 SUBHASH S. PIDAPARTHI, CRAIG S. LENT (2018). Exponentially Adiabatic Switching in
Quantum-Dot Cellular Automata. Journal of Low Power Electronics and Applications 8:1-15.
 SAEED MIRZAJANI OSKOUEI, ALI GHAFFARI (2019). Designing a new reversible ALU by
QCA for reducing occupation area.The Journal of Supercomputing 75(8):5118-5144.
 KIANPOUR M, SABBAGHI-NADOOSHAN R Novel 8- bit reversible full adder/subtractor
using a QCA reversible gate. JComput Electron 16(2):459–472, 2017.
 TAHERKHANI E, MOAIYERI MH, ANGIZI S (2017) Design of an ultra-efficient reversible full
adder-subtractor in quantum-dot cellular automata. Optic 142:557–563
 BARUGHIYZ, HEIKALABAD SR, A three-layer full adder/subtractor structure in quantum-
dot cellular automata. Int JTheor Phys 56(9):2848–2858, 2017.
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 15

16.  FIRDOUS AHMAD, SUHAIB AHMED,VIPAN KAKKAR, MOHIUDDIN BHAT, ALI NEWAZ BAHAR, SHAHJAHAN
WANI, “Modular Design of Ultra-Efficient Reversible Full Adder-Subtractor in QCA with Power Dissipation
Analysis”,2018. Int JTheor Phys. https://doi.org/10.1007/s10773-018-3806-3.
 MD. ABDULLAH-AL-SHAFI AND ALI NEWAZ BAHAR , “An Architecture of 2-Dimensional 4-Dot 2-Electron QCA
Full Adder and Subtractor with Energy Dissipation Study. Active and Passive Electronic Components”, Hindawi
5062960: 1-10 2018. https://doi.org/10.1155/2018/5062960.
 PANDIAMMAL KP, D. MEGANATHAN-“Efficient design of QCA based hybrid multiplier using clock zone based
crossover”, Springer, January 2020,Analog Integrated Circuits and Signal Processing 102(3), DOI:
10.1007/s10470-019-01570-3.
 JUNJUN HUANG, S. LALE, “A novel Nano-scale architecture ofVedic multiplier using majority logic in quantum-
dot cellular automata technology”, ELECTRONICS LETTERS, August 2022,Vol. 58 No. 17.
 VAIBHAV JAINVAIBHA, JAINDEVENDRA KUMAR SHARMAHARI, and MOHAN GAURHARI –“Area and energy
optimized multilayer QCA-based 4N-bit scalable multiplier (M4N-MUL)”, November 2022 European Physical
Journal plus 137(11), DOI: 10.1140/epjp/s13360-022-03486.
 KHAMALESH KUMAR PADMANABHAN, UMADEVI SEERENGASAMY and ABRAHAM SUDHARSON PONRAJ–
“High-Speed Grouping and Decomposition Multiplier for Binary Multiplication”, Electronics 2022, 11, 4202.
https://doi.org/10.3390/electronics11244202.
INTERVIEW FOR Ph.D. ADMISSION FOR JANUARY 2022 SESSION 16

17.  Presented a paper on the title “A NOVEL AREA EFFICIENTTIEO
BASED REVERSIBLE LOGIC GATES IN QCA PARADIGM” in the 3rd
InternationalConference on Pervasive Computing and Social
Networking, 19-20, June 2023.
 Presented a paper on the title, “Context Monitoring of Patients Using
Wireless Network", in the InternationalConference on Inventive
ComputationTechnologies (ICICT 2023), 26-28,April 2023 atTribhuvan
University, Nepal.
INTERVIEW FOR Ph.D. ADMISSION FOR JULY 2023 SESSION 17

18.  Presented a paper on the title, “Black box for Automobiles", in the 8th
International conference on Science, Engineering andTechnology(ICSET-
2023) , 4th March 2023
 Conducted value added course on “cadence”.
 Delivered seminars onVLSI.
INTERVIEW FOR Ph.D. ADMISSION FOR JANUARY 2022 SESSION 18