This provides information related to ARM Cortex-M4 features , Modes, Registers etc. I have discussed importance of multiple stack pointers and privilege levels. STM32 Nucleo-L4R5ZI board is taken for this case study.

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ARM
Cortex-M4
Registers

2. ARM Use cases
●
●
ISA ARMv7-M ARMv7E-M ARMv8-A
Instruction Set Thumb/Thumb-2 Thumb/Thumb-2 AARCH32/AARCH6
4
DSP Yes Yes Yes
FPU VFP4 SP
optional
VFP5 SP & DP
optional
VFP4
Cache Optional I-cache, D-cache L1 /core L2-shared
NEON SIMD Yes
Trustzone Yes
Virtualization Yes
MMU Yes
Core/CPU-
Implementation
Cortex-M4 Cortex-M7 Cortex-A53
Eval Board STM32 Nucleo I.Mx 1050RT BCM2837B0 SoC
(Raspberry-PI)

3. Cortex-M4@STM32
●
●
Remarks
Mode Thread Handler After Reset, CPU will have
Thread Mode
Privilege Level Unprivileged Privileged Unprivileged level will have
limited access
Stack Pointer MSP or PSP MSP SP in Thread Mode can be
configured using CONTROL
Register
● User application will run in Thread mode. If any interrupt or exception event
occurs, It will automatically enters in Handler mode. After executing Interrupt
Service Routine, It will return to Thread mode
● Different privilege levels helps in defining user application access limits
● Two stack pointers help in protecting OS stack from application and also
helps in managing mult-task application

4. Cortex-M4 Registers@STM32
●
Registers for data manipulation in
ALU
●
Low Registers can be accessed by all
instructions
●
High Registers not accessible by all
16-bit encoded instructions.
●
Stack Pointer- Runtime temporary
data memory Pointer
●
Link Register – Receives return
address from PC whenever BL and
Blx instruction executed. Also used
for exception return
●
Program Counter -Runtime
Instruction Memory Pointer
●
Registers (r0-r12), PSP, LR and PC
can be accessed with unprivileged
level as well.

5. Cortex-M4 registers...
●
XPSR
–
APSR -Application program status register .It can
be accessed from unprivileged level as well
●
Flags from previous instructio executions
–
IPSR - Interrupt program status register
●
Number of the current ISR
–
EPSR -Execution program status register
–
Thumb state bit, and the execution state bits for
either the:
●
If-Then (IT) instruction
●
Interruptible-Continuable Instruction (ICI)
●
CONTROL
–
FPCA – Floating Point Context Active
–
SPSEL- MSP or PSP
–
nPRIV -Thread mode Privilege
●
MSP – Handler Mode always use this. By default, MSP
is being used in both Handler and Thread modes
●
PSP- Thread Mode can be configured to use MSP or
PSP using CONTROL register

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THANKS
If you found this information useful Please like
this video AND subscribe to
www.youtube.com/embedkari
Embedded Career Information :
www.facebook.com/embedkari
Website:www.embedkari.com