RISC and CISC architectures and
design issues
• 33-Talha Momin
• 34-Sugam Pandey
• 35-Atharva Parab
• 36-Simran Pardeshi

RISC
Reduced Instruction
Set Architecture
The Sun Microsystems UltraSPARC
processor is a type of RISC microprocessor.

What is RISC?
• Reduced Instruction Set Computer is a type of microprocessor
architecture that utilizes a small, highly-optimized set of instructions
rather than the highly-specialized set of instructions typically found
in other architectures.
• RISC is an alternative to the Complex Instruction Set Computing
(CISC) architecture and is often considered the most efficient CPU
architecture technology available today.
• With RISC, a central processing unit (CPU) implements the
processor design principle of simplified instructions that can do less
but can execute more rapidly. The result is improved performance.

Characteristics of RISC
• Simpler instruction, hence simple instruction decoding.
• Instruction comes undersize of one word.
• Instruction takes a single clock cycle to get executed.
• More general-purpose registers.
• Simple Addressing Modes.
• Less Data types.
• Pipeline can be achieved.

CISC
Complex Instruction Set Computer

What is CISC?
● The CISC architecture tries to reduce the number of Instructions that a program has, thus
optimizing the Instructions per Program part of the above equation. This is done by
combining many simple instructions into a single complex one.
● The CISC architecture can be better explained with the analogy of a dog:
● In the dog analogy, “Fetch” can be thought of as a CISC instruction. When a dog
“Fetches” a ball, it is actually doing a series of instructions that include: “Follow the ball”
then “Pick it up” followed by “Go back to human” and finally, “Give human the ball”.
● It is obvious that giving a dog a single “fetch” instruction is easier and faster than giving it
four separate instructions. And this is why initial CPU manufacturers like Intel designed
CISC processors.

Characteristics of CISC
 Since the instructions are complex the decoding is complex as well.
 Instructions are larger than one-word size.
 Instruction may take more than a single clock cycle to get executed.
 Less number of general-purpose registers as the operation gets performed in
memory itself.
 Complex Addressing Modes.
 More Data types.

RISC
o RISC tries to reduce the time taken for each
instruction to execute.
o In RISC however, since all instructions take
one cycle, pipelining instructions is easier.
o Transistors are used for more registers.
o Can perform only Register to Register
Arithmetic operations.
o Requires more number of registers
CISC
o While CISC tries to complete an
action in as lines of assembly code as
possible
o CISC instructions take a more
number of cycles to execute,
parallelism and pipelining of
instructions is much harder.
o Can perform REG to REG or REG to
MEM or MEM to MEM
o Requires less number of registers

Example

X
Y
1 2 3 4
1
2
3
4
RA
R B
Memory
Register Set
Execution Unit
In CISC:
• MULT 2:2, 3:3
x , y
• X=x*y
In RISC:
• LOAD A, 2:2
• LOAD B, 3:3
• PROD A,B
• STORE 2:2,A

Applications in real life:
• Intel and AMD’s processor’s till this day use CISC architecture.
• A very recent example of RISC architecture being used are Apple’s self
designed ARM based M1 chips which are their most powerful and
performance efficient chips so far.
• By the beginning of the 21st century, the majority of low-end and mobile
systems relied on RISC architectures. Examples include:
• The ARM architecture dominates the market for low power and low cost
embedded systems. It is used in a number of systems such as most
Android-based systems, the Apple iPhone and iPad, Microsoft Windows
Phone, Nintendo Game Boy Advance, DS, 3DS and Switch, Raspberry
Pi, etc.
• IBM's PowerPC was used in the GameCube, Wii, PlayStation 3, Xbox
360 and Wii U gaming consoles.
• The world’s fastest super computer Fugaku is also based on ARM
architecture which itself is a family of RISC.

Conclusion
● As you can might have learned both the architectures have actually come a long
way since their inception.
● In today’s modern world CPU technology has come so far that CISC and RISC
barely have any difference in performance.
● Execution speed now depends heavily upon caching. CPU speeds have indeed
risen—to the point that clock speed is limited almost entirely by power
consumption which limits RISC and CISC designs to roughly the same clock
speeds.
● Thus that much explains how RISC and CISC are now roughly at technical
parity.