Introduction to Low power VLSI

1. Unit – 1
Low Power Requirements
Historical background

2. Contents
• Historical background
• Requirements for low power
• Sources of power dissipation
Dynamic power
Static power
• Low power design methodologies

3. Introduction
• In the present era of VLSI design for low power is one of the
major concerns in complex integrated circuits.
• In deep submicron technology (from 130 nm) onwards, poses
a new set of design problems related to the power
consumption of the chip.
• Due to higher levels of integration density, tens of millions of
gates are being implemented on a relatively small die.
• This leads to increase in power density and total power
dissipation.

4. Introduction
• As the technology has scaled down to 90 nm and below, the
leakage current has increased in an exponential manner.
• At lower technology nodes like from 65-nm designs, leakage
power dominates the dynamic power.
• Due to increase in power density limits the max operating
frequency and reliability.
• Hence different techniques to reduce the power dissipation at
various levels of design abstractions are used.

5. Historical background
• In 1947 the transistor is invented by William Shockley and his
colleagues at Bell Laboratories, which is the beginning point in
the “solid state” era of electronic circuits and systems.
• Within few years after the invention, transistors were
commercially available.
• The advantages of transistor over vacuum tube are
1. Smaller size
2. lower power consumption
3. higher reliability
• Later on the research engineers of Fairchild developed the
first planner transistor in the late 1950s, which was the key to
the development of integrated circuits (ICs) in 1959.

6. Historical background
• Planner technology allowed realization of a complete
electronic circuit having a number of devices and
interconnecting them on a single silicon wafer.
• Goorden Moore of Intel had predicted the transistor density
in an integrated circuit doubles for every 24 months called as
Moore’s law.
• Figure 1.1 shows the integrated density over a period of time.
Year Processor # of Transistors
1971 Intel 4004 2300
1976 8085 6500
1978 8086 29,000
1985 80386 2,75,00
1989 80486 12,00,000
1993 Pentium 33,00,000

7. Historical background
• Based on the very few empirical data, he predicted that by
1975, it would be possible to cram as many as 65,000
components onto a single silicon chip of about one fourth of a
square inch.
• Later in the year 1975, Moore revised that transistor density
doubles for every 18 months.
• Again after 30 years, Moore compared the actual
performance of two kinds of devices random-access
memories (RAM) and microprocessors.
• It is observed that, the trend followed the previous trend.

8. Evolution of IC Technology
• Based on the scale of integration, the IC technology can be
divided into five different categories, as given in Table 1.1.

9. Evolution of IC Technology
• The first half of the 1960s was the era of small-scale
integration (SSI), with about ten planner transistors on a chip.
• The SSI technology led to the fabrication of gates and flip-
flops.
• In the second half of the 1960s, counters, multiplexers,
decoders, and adder were fabricated using the medium-scale
integration (MSI) technology having 100–1000 components on
a chip.
• The 1970s was the era of large-scale integration (LSI)
technology with 10,000–20,000 components on a chip
producing typical products like 8-bit microprocessor, RAM,
and read-only memories (ROM).

10. Evolution of IC Technology
• In the 1980s, VLSI with about 20,000–50,000 components led
to the development of 16-bit and 32-bit microprocessors.
• Beyond 1985 is the era of ultra-large-scale integration (ULSI)
with more than 50,000 devices on a chip, which led to the
fabrication of digital signal processors (DSPs), reduced
instruction set computer (RISC) processor, etc.
• In 1971, Intel marketed a general-purpose digital system
named as 4004. It was a 4-bit CPU (Microprocessor).
• Thus, the microprocessor is a “CPU on a chip”.
• Later on Intel developed 8-bit microprocessors 8008 and 8085
• Other semiconductor device manufacturers such as Motorola
and Zilog produced more and more powerful
microprocessors.

11. Evolution of IC Technology
In the past three decades, the evolution tree of microprocessors has grown into a
large tree with three main branches as shown in Fig. 1.2.

12. Evolution of IC Technology
• The main branch represents the general-purpose
microprocessors, which are used to build computers of
different kinds such as laptops, desktops, workstations,
servers, etc.
• The fruits of this branch have produced high performance
CPUs with increased processing capability starting from 4-bit
processors to the 64-bit processors.
• The clock rates increased from few megahertz to thousands of
megahertz and advanced architectural features incorporated
like
• Pipelining Superscalar architecture
• on-chip cache memory dual core

13. Evolution of IC Technology
• The left branch represents a variant of microprocessor known
as microcontrollers.
• A microcontroller can be considered a “computer on a chip.”
• Apart from the CPU, other subsystems such as ROM, RAM,
input/output (I/O) ports, timer, and serial port are
incorporated on a single chip in a microcontroller.
• Microcontrollers are typically used to realize embedded
systems such as toys, home appliances, intelligent test and
measurement equipment, etc.
• The branch on the right side represents special-purpose
processors such as DSP microprocessors (TMS 320), network
processors (Intel PXA 210/215), etc.

14. Evolution of IC Technology
• These special-purpose processors are designed to enhance
performance of special applications such as signal processing,
router and packet-level processing in communication
equipment, etc.
• With the increase in the number of transistors, the power
dissipation also increasing as shown in Fig. 1.4.
• This forced the chip designers to consider low power as one of
the design parameters apart from performance and area.
Technology Processor # of Transistors
14 nm Core i3 2300
14 nm Core i5 6500
10 nm Core i7 10 nm
14 nm Core i9 2,75,00

15. Requirements for low power
• Due to aggressive device size scaling has created problems in
– yield
– reliability
– testing
• As a consequence, there is a change in the trend of specifying
the performance of a processor.
• Power consumption is now considered one of the most
important design parameters.

16. Requirements for low power
• Until recently, performance of a processor related with circuit
speed or processing power, e.g., million instructions per
second (MIPS) or million floating point operations per second
(MFLOPS).
• Power consumption was of secondary concern in designing
ICs.
• However, in nanometer technology, power has become the
most important issue because of:
– Increasing transistor count
– Higher speed of operation
– Greater device leakage currents

17. Important Factors
• The important factors considered to make power dissipation
as major constraint are.
• 1. Continues shrinking of the device dimensions to improve
the performance leads to integration density.
• 2. As a consequence, the magnitude of power per unit area
known as power density is increasing as shown in Fig. 1.5.

18. Important Factors
• 3. To remove the heat generated by the device, it is necessary
to provide suitable packaging and cooling mechanism.
• 4. To make a chip commercially viable, it is necessary to
reduce the cost of packaging and cooling, which in turn
demands lower power consumption.
• 5. Increased customer demand of hand-held, battery-
operated devices such as cell phone, personal digital assistant
(PDA), palmtop, laptop, etc.
• 6. users of portable equipment for increased functionality (as
provided by smart phones) along with long battery life.

19. Important Factors
• 7. As these devices are battery operated, battery life is of
primary concern. Commercial success of these products
depends on size, weight, cost, computing power, and above all
on battery life.
• 8. The reliability is closely related to the power consumption
of a device.
• 9. As power dissipation increases, the failure rate of the
device increases because temperature-related failures start
occurring with the increase in temperature as shown in Fig.
1.6.

20. Important Factors
• 10. It has been found that every 10 ºC rise in temperature
roughly doubles the failure rate. So, lower power dissipation
of a device is essential for reliable operation.
Different failure mechanisms against temperature
0 100 200 300
ᵒC above normal operating temperature
Thermal runaway
Gate Dielectric
Junction diffusion
Electromigration diffusion
Electrical parameter shift
Package related failure
Silicon interconnect fatigue

21. Summary
• According to an estimate of the US Environmental Protection
Agency (EPA), 80 % of the power consumption by office
equipment is due to computing equipment and a large part
from unused equipment.
• Power is dissipated in the form of heat.
• The cooling techniques transfer the heat to the environment.
• To reduce adverse effect on environment, efforts such as EPA’s
(Environmental Protection Agency, USA) Energy Star program
leading to power management standard for desktops and
laptops has emerged.

22. Energy Star
• What Is an Energy Star Rating?
• Energy star ratings indicate that a product meets federally
mandated guidelines regarding energy efficiency.
• Though not all appliances come with an Energy Star Rating,
many do, which contribute to sustainability.
• Example:
• ENERGY STAR refrigerators are excellent options because they
use less energy and save money over time

23. Sources of Power Dissipation
• What is the difference between power and energy?
• Power: instantaneous power in the device
• Energy: the integration of power with time
• Figure 1.7 illustrates the difference between the power and
energy
Fig. 1.7 Power versus energy

24. Power versus Energy
• Approach 1 takes less time but consumes more power than
approach 2.
• But the energy consumed by the two, that is, the area under
the curve for both the approaches is the same, and the
battery life is primarily determined by this energy consumed.

25. Energy versus power
• For work to be done, a force must be exerted and there must
be motion or displacement in the direction of the force.
• Energy is the capacity to do some physical activities or work,
such as running, jumping, etc., while power is defined as the
rate at which the energy is transferred, or the work is
completed.
• The unit used to measure energy is joules.
• Power is measured in watts.
• P = E / t
• P – Power
• E- Energy t – Time taken

26. Peak power and Average Power
• Power dissipation is measured commonly in terms of two
types of metrics:
• Peak power: Peak power consumed by a particular device is
the highest amount of power it can consume at any time. The
high value of peak power is generally related to failures like
melting of some interconnections and power-line glitches.
• Average power: Average power consumed by a device is the
mean of the amount of power it consumes over a time period.
• High values of average power lead to problems in packaging
and cooling of VLSI chips.

27. Static power and Dynamic Power
• In order to develop techniques for minimizing power
dissipation, it is essential to identify various sources of power
dissipation and different parameters involved in each of them.
• The total power for a VLSI circuit consists of two components
1. dynamic power 2. static power
• Dynamic power is the power consumed when the device is
active, that is, when signals are changing values.
• Static power is the power consumed when the device is
powered up but no signals are changing value.

28. Sources of Power Dissipation
• In CMOS devices, the static power consumption is due to
leakage mechanism. Various components of power dissipation
in CMOS devices can be categorized as shown in Fig. 1.8.

29. Dynamic Power
• Dynamic power is the power consumed when the device is
active, that is, when the signals of the design are changing
values.
• It is generally categorized into three types:
• Switching power
• Short-circuit power
• Glitching power

30. Switching Power
• The first and primary source of dynamic power consumption
is the switching power.
• This is the power required to charge and discharge the output
capacitance on a gate.
• Figure 1.9 illustrates switching power for charging a capacitor.
The energy per transition
is given by

31. Measurement of Dynamic Power
Case 1: Consider low-to-High transition
How much of energy EVDD is taken from the power supply?
Integrating instantaneous power over the period of interest.

32. Due to charging/discharging:
The energy stored across the capacitor (Ec) is = Integrating
instantaneous power over the period of interest
= Energy stored in the Capacitor at
the end of the transition.

33. Dynamic power during Charging cycle
• Energy delivered from supply is CL VDD
2
• Energy stored in the capacitor is ½ CL VDD
2
• Remaining ½ CL VDD
2 energy is dissipated in the
form of heat across the PMOS ON resistance
How much of energy is delievered by
the power supply?
Energy stored in the Capacitor at
the end of the transition.

34. Switching Power
• where CL is the load capacitance
• Vdd is the supply voltage.
• Therefore, Switching power is expressed as:
• Where f is the frequency of transitions
• Ptrans is the probability of an output transition
• fclock - frequency of the system clock.
• Now if we take:
• Then

35. Switching Power : Conclusion
• 1. Switching power is not a function of transistor size
• 2. dependent on switching activity and load capacitance.
• 3. Switching power is data dependent.
• In addition to the switching power dissipation for charging
and discharging the load capacitance, switching power
dissipation also occurs for charging and discharging of the
internal node capacitance.
• Thus, total switching power dissipation is given by
• where αi and Ci are the transition probability and capacitance,
respectively, for an internal node i.

36. Short circuit Power
• Figure 1.10 illustrates short-circuit currents.
• Short-circuit currents occur when both the NMOS and PMOS
transistors are on.

37. Short circuit Power / Switching power
• Now we consider that input takes some finite time to change,
similarly output
• So, both transistors are ON for a finite time
• This causes a direct current path between VDD and GND
tsc – time for both devices are conducting

38. Dissipation due to direct path currents
The energy consumed per switching period
(Both L H and H  L transition) is
Average power consumption :
It is actually VDD multiplied by the Area of the triangle
Csc – Short circuit capacitance
Capacitive (dynamic)
tsc = Rsc * Csc
tsc = VDD / Ipeak * Csc

39. Calculating the Time interval
ts = 0 – 100 % transition time
For a linear time input slope, this time can be approximated to
Let, Vtn = - Vtp = VT
Y = mX (straight line)
m - slope / slew
m= Y/X = VDD / ts -- (1)
Also, m =
(VDD +Vtp – Vtn) / tsc
Equating the two,
VDD / ts = (VDD – 2VT) / tsc
m = (VDD – 2VT) / tsc
trise = 0.8 * ts
trise = 10 – 90 %
transition time
-- (2)

40. Short circuit Energy
tr(f) – denotes rise / fall time
------ (1)
------ (2)
------ (3)
Assuming triangle has
equal rise and fall time

41. Short circuit power from Energy
• Short circuit power can be calculated by applying the
Tsc (Time interval at which both devices are ON)
value in to the power equation
• Just like dynamic power, this is a transient
phenomenon
• Only when the input is making change it will happen
• So we need to consider clock frequency, activity
factor,

42. Short circuit Power
• Let Vtn be the threshold voltage of the NMOS transistor and
Vtp is the threshold voltage of the PMOS transistor.
• Then, in the period when the voltage value is between Vtn
and Vdd–Vtp, while the input is switching either from 1 to 0 or
vice versa, both the PMOS and the NMOS transistors remain
ON, and the short-circuit current follows from Vdd to ground
(GND).
• The expression for short-circuit power is given by

43. Short circuit Power
• Where, tsc - rise/fall time duration of the short-circuit current
• Ipeak - total internal switching
• μ - mobility of the charge carrier
• εox - permittivity of the silicon dioxide
• W - width
• L - length
• D - thickness of the silicon dioxide

44. Short circuit Power : Summary
• The following conclusions are derived from the above
equation
• The short-circuit power dissipation depends on the supply
voltage, rise/fall time of the input and the clock frequency
apart from the physical parameters.
• So the short-circuit power can be kept low if the ramp
(rise/fall) time of the input signal is short for each transition.
• Then the overall dynamic power is determined by the
switching power.

45. Glitching Power
• The glitching power arises due to finite delay of the gates.
• Glitches often occur when paths with unequal propagation
delays converge at the same point in the circuit.
• Glitches occur because the input signals to a particular logic
block arrive at different times, causing a number of
intermediate transitions to occur before the output of the
logic block stabilizes.
• These additional transitions result in power dissipation, which
is categorized as the glitching power.

46. Hazard
#5
#5
#5
#3
Initially, X1, X2, X3 = 111
Hence, Y = 1
Now, if X2 changes from 1  0, Y makes an
intermediate ‘0’ transition, finally reaches ‘1’.
Since the dynamic power is directly proportional to the number of output transitions
of a logic gate, glitching can be a significant source of signal activity and deserves
mention here.

47. 4. Dynamic / glitching transitions
• we ignored the fact that the gates have a non-zero
propagation delay.
• The finite propagation delay from one logic block to the
next can cause spurious transitions, called glitches,
critical races, or dynamic hazards

48. Example : Dynamic / glitching transitions
A chain of NAND gates for all inputs going simultaneously
from 0 to 1 (Input side).
Initially, all the outputs are 1 since one of the inputs was 0.
For this particular transition, all the odd bits must transition
to 0 while the even bits remain at the value of 1.
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

49. Hazard

50. Static Power
• Definition :
• Static power dissipation takes place as long as the device is
powered ON, even in the absence of signal changes.
• In CMOS circuits, in the steady state, there is no direct path
from Vdd to GND and so there should be no static power
dissipation.
• But there are various leakage current mechanisms which are
responsible for static power dissipation.
• Since the MOS transistors are not perfect switches, there will
be leakage currents and substrate injection currents, which
will give rise to static power dissipation in CMOS.

51. Static Power
• Leakage currents are also normally negligible, in the order of
nano-amps, compared to dynamic power dissipation.
• With deep submicron technologies, the leakage currents are
increasing drastically to in 90-nm technology and thereby
leakage power also has become comparable to dynamic
power dissipation.
• Intel Pentium 4 with 90 nm manufacturing technology
introduced in the year 2004 for general purpose computing.
• Intel Core 2 Duo processor with 65 nm manufacturing
technology introduced in the year 2006 for Embedded
applications

52. Static Power
• Figure 1.11 shows several leakage mechanisms that are
responsible for static power dissipation.

53. Leakage currents in MOSFET
• Figure 1.11 shows several leakage mechanisms that are
responsible for static power dissipation.
• I1 - reverse-bias p–n junction diode leakage current
• I2 - reverse-biased p–n junction current due to tunneling
• of electrons in the valence band of the p region to the
• conduction band of the n region
• I3 - subthreshold leakage current between the source
• and the drain when the gate voltage is less than Vth
1
2
3

54. Leakage currents in MOSFET
• I4 - oxide tunneling current due to reduction in the oxide thickness
• I5 - gate current due to hot carrier injection of electrons (High Vds & Vgs)
• I6 - gate-induced drain leakage current due to high field effect in the drain
junction
• I7 - channel punch through current due to close proximity of the drain and
the source in short-channel devices.
4
5
6
7

55. Leakage currents in MOSFET

56. Leakage currents in CMOS Inverter
• The short circuit power dissipation model of CMOS inverter is
illustrated in figure 1.12.

57. Low power design methodologies
• Low-power design methodology needs to be applied
throughout the design process starting from system level to
physical or device level.
• Various approaches can be used at different level of design
hierarchy.
• This reduction in power dissipation with supply voltage
scaling comes at the expense of performance.
• It is essential to devise suitable mechanism to contain this loss
in performance due to supply voltage scaling for the
realization of low-power high-performance circuits

58. Low power design methodologies
• The loss in performance can be compensated by using
suitable techniques at the different levels of design hierarchy
are
• physical level
• logic level
• architectural level
• system level

59. Techniques
• The different techniques adopted are:
• 1. device feature size scaling
• 2. parallelism and pipelining
• 3. architectural-level transformations
• 4. dynamic voltage, and frequency scaling.
• Apart from scaling the supply voltage to reduce dynamic
power, another alternative approach is to minimize the
switched capacitance comprising the intrinsic capacitances
and switching activity.

60. Techniques
• In CMOS digital circuits, the switching activity can be reduced
by
• 1. algorithmic optimization
• 2. architectural optimization
• 3. use of suitable logic-style
• 4. Logic-level optimization
• The intrinsic capacitances of system-level busses are usually
several orders of magnitude larger than that for the internal
nodes of a circuit.
• As a consequence, a considerable amount of power is
dissipated for transmission of data over I/O pins.

61. Techniques : Clock gating
• It is possible to save a significant amount of power reducing
the number of transactions, i.e., the switching activity, at the
processors I/O interface.
• One possible approach for reducing the switching activity is
to use suitable encoding of the data before sending over the
I/O interface.
• The switching activity can also be reduced by using the sign-
magnitude representation in place of the conventional two’s
complement representation.
• Switching activity can be reduced by judicious use of clock
gating, leading to considerable reduction in dynamic power
dissipation.

62. Techniques : Logic style
• Instead of using static CMOS logic style, one can use other
logic styles such as pass-transistor and dynamic CMOS logic
styles or a suitable combination of pass-transistor and static
CMOS logic styles to minimize energy drawn from the supply.
• Although the reduction in supply voltage and gate
capacitances with device size scaling has led to the reduction
in dynamic power dissipation, the leakage power dissipation
has increased at an alarming rate because of the reduction of
threshold voltage to maintain performance.
• As the technology is scaling down from submicron to
nanometer, the leakage power is becoming a dominant
component of total power dissipation.

63. Techniques : Logic style
• Leakage reduction methodologies can be broadly classified
into two categories, depending on whether it reduces standby
leakage or runtime leakage.
• There are various standby leakage reduction techniques such
as :
• Input vector control (IVC)
• body bias control (BBC)
• multi-threshold CMOS (MTCMOS)
• Runtime leakage reduction techniques such as
• static dual threshold voltage CMOS (DTCMOS) technique
• adaptive body biasing
• dynamic voltage scaling

64. Thank You

65. Evolution of IC Technology
• Figure 1.3 shows the series of microprocessors produced by
Intel in the past three-and-a-half decades conforming to
Moore’s law very closely.

66. • Merced was the first Itanium microarchitecture
designed by Intel.
• The architecture avoids expensive out-of-order
execution hardware by moving scheduling
responsibilities to the compiler.
• The DTLB translates the 32-bit linear address
produced by the load or store unit into a 36-bit
physical memory address before the cache lookup is
performed.

67. Mercedes Microarchitecture - Intel

68. 10 stage Pipeline
• 10 stage pipeline
– IPG: Get next instruction pointer
– FET: Fetch from instruction cache
– ROT: Instruction rotation, decoupling buffer
– EXP: Instruction dispersal
– REN: Register remapping
– WLD: Word line decode
– REG: Register file read
– EXE: Execute
– DET: Exception detection
– WRB: Writeback

69. Pipelining
• The pipeline is a "logical pipeline" that lets the processor
perform an instruction in multiple steps.
• Pipelining is a technique where multiple instructions are
overlapped during execution.
• The processing happens in a continuous, orderly, somewhat
overlapped manner.
• The name "pipeline" comes from a rough analogy with
physical plumbing in that a pipeline usually allows
information to flow in only one direction, like water often
flows in a pipe.

70. Pipelining
• The classic five stage RISC pipeline
• Instruction fetch.
• Instruction decode.
• Execute.
• Memory access.
• Writeback.

72. Superscalar architecture
• Simply put, a pipeline starts the execution of the next
instruction before the first has completed - but instructions
are executed still in series and in order.
• A superscalar architecture can start two or more instructions
in parallel in one core, and independent instructions may get
executed out-of-order.
• This would enable the dispatch unit to keep both the integer
and floating point units busy most of the time. In general,
high performance is achieved if the compiler is able to
arrange program instructions to take maximum advantage of
the available hardware units.

73. Superscalar architecture

74. on-chip cache memory
• A cache is a smaller, faster memory, located closer to
a processor core, which stores copies of the data from
frequently used main memory locations.
• A cache's primary purpose is to increase data retrieval
performance by reducing the need to access the underlying
slower storage layer.
• So instructions and data can be read from it (and written to it)
much more quickly than is the case with normal RAM

75. L1, L2 and L3 cache
• L1 cache, or primary cache, is extremely fast but relatively
small, and is usually embedded in the processor chip as CPU
cache.
• L2 cache, or secondary cache, is often more capacious than
L1. ...
• Level 3 (L3) cache is specialized memory developed to
improve the performance of L1 and L2.

76. Dual core
• A dual-core processor is a CPU with two processors or
"execution cores" in the same integrated circuit.
• Each processor has its own cache and controller, which
enables it to function as efficiently as a single processor.
• However, because the two processors are linked together,
they can perform operations up to twice as fast as a single
processor can.
• Quad-cores are usually better than dual-cores and hexa-cores
better than quad-cores, and so on

79. Work -Formula
• W = F * cos Θ = F * D Joules.
• Where W is the work done,
• F is the force,
• d is the displacement,
• θ is the angle between force and displacement and F cosθ is
the component of force in the direction of displacement.
• The unit of Energy is the same as of Work, i.e. Joules.

80. Power -Formula
• We can define power as the rate of doing work, and it is the
amount of energy consumed per unit of time.
• Therefore, it can be calculated by dividing work done by time.
• P = Work / time = Energy / time
• Where P – Power
• W is the work done,
• E is the Energy,
• t is the time taken

81. Diode Leakage Current
• When a semiconductor device is reverse biased it should not
conduct any current, however, due to an increased barrier
potential, the free electrons on the p side are dragged to the
battery's positive terminal, while holes on the n side are
dragged to the battery's negative terminal.

82. Reverse Biased Tunneling Current
• The breakdown effect can be related to two different physical
phenomena.
• The first one is a tunneling effect called the Zener effect.
• The presence of a high electric field (~106V/cm for silicon)
creates electron-hole pairs.
• The electrons associated to these pairs are emitted through
the depletion zone, from the valence band to the conduction
band, without loss or gain in energy, hence the term of
tunneling used for this effect.
• In practice, one may observe the Zener effect only for highly-
doped PN junctions, in which the space charge zone is
narrow so that the “tunnel” is short enough to be crossed.

83. Tunneling Effect
• When the reverse voltage is increased, the electric field is increased
accordingly inside the junction.
• But the electric field cannot exceed a given value.
• This is because as the electric field increases, so does the electrostatic
force acting on the electrons linked to the crystalline network
F = - q E (F – Force, E – Electric field)
• This force can at some point become so high that it exceeds the binding
force linking the valence electrons to their respective nuclei.
• As these electrons are released, the crystal becomes conductive and
neither the electric field nor the voltage can increase any more.
• This means that the maximum electric field that can be applied to a
semiconductor crystal is the field that would lead to the direct excitation
of an electron from the valence band to the conduction band, or stated
differently the field leading to the material ionization.

84. Hot carrier injection
• Hot Carrier Injection occurs at the drain extension due to high
electric field causing interface states that trap charges that
increases Vth .

85. Gate Induced Drain Leakage
• Gate-induced drain leakage current is due to the band-to-
band tunneling process in silicon in the gate-to-drain overlap
region. This drain leakage current increases with increasing Vd
and decreasing Vg.
• GIDL(Gate Induced Drain Leakage) is directly proportional to
the gate-drain overlap area.

86. Drain induced barrier lowering
• When we apply a positive voltage to the Drain of the short
channel device, the threshold voltage (Vth) will be reduced
due to the depletion region under the drain region, and
overall channel length will reduce
• This is called Drain induced barrier lowering (DIBL)
• Also called short channel effect in CMOS

87. Channel Punchthrough in MOSFET
• Punch through is addressed to MOSFETs' channel length
modulation and occurs when the depletion regions of the
drain-body and source-body junctions meet and form a
single depletion region.