2. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Sr.No TABLE OF CONTENTS
1 Design Specifications and Introduction
2 Stabilty Analysis
3 Ideal Biasing Circuit Analysis
4 Choosing Gamma S
5 Choosing Gamma L
6 Ideal Circuit with IO matching
7 Design using full parasitic models
Modelithic Model
Complete Schematic using TL
8 Physical Layout
9 Fabricated Design
10 Summary
3. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Design Specifications and Introduction:
Specification GOAL
Fc (GHz) 1.9
% Bandwidth 20
Gain (dB) 14 +/- 1.5
NF max (dB) 2
Input RL (dB) >12
Output RL (dB) >20
Stability Unconditional
Zo (Ohms) 50
A Low Noise Amplifier is to be designed and fabricated using practical (BJT) amplifier and
lumped components. The final simulated design is to be made using Modelithics components
which contained parasitics of every lumped elements and transistor. The designing of this
amplifier was done is 3 stages.
Firstly, the ideal schematic for the amplifier (BJT_INF_BFP420_MDLXNLT1) was generated
using the proper biasing condition. The simulation is compared with the goals given above and
the optimized accordingly. Taking in to consideration than the transistor as an amplifier is
unconditionally stable in the 20% bandwidth of given cut-off frequency.
Secondly, the ideal components were then replaced using Modelithics components which
considers the parasitics of the practical components making the design more realistic and the
components values are again optimized to get the required goals.
Lastly, the Modelithics schematic is then used to generated the layout, which is then than used to
create the actual circuit on the FR4 substrate and final measurements were taken. The details
explanation of every stage is given below. In the next we pages, I outline the design procedure I
followed and also discuss the results at every stage.
The files used for each case are mentioned in the parenthesis besides the heading in each section
of the report.
4. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Stability Analysis:
This section involves choosing the biasing values.
i). BIASING OF BJT: (bjt_biasing.dsn)
ii). STABILITY ANALYSIS: (ideal_biasing _circuit.dsn)
5. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Resistive loading technique was used at the output to make the potentially unstable transistor
unconditionally stable. The resistor at output was used and it was connected at the output because
it gave a lesser noise. Resistor introduces noise in a RF circuit and hence it is always better to have
it at the output to reduce noise. By increasing the output resistor, the gain increased but the stability
decreased. So the value of output resistor was carefully to obtain a compromise between gain and
noise figure.
Stability factor K>1 Stability measure B<1
7. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Ideal Biasing Circuit analysis (ideal_biasing _circuit.dsn):
The preliminary gain and noise figure analysis was done .
i) Maximum Gain:
8. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
ii) Noise Figure:
9. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Choosing the Gamma_S : (ideal_biasing _circuit.dsn)
The value of Gamma_S was chosen as shown below in implement input matching network and
calculated corresponding Г out and ГL value such that Гout=ГL* and VSWRout=1.
10. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Choosing Gamma_L:
Gamma_L can be determined by first finding Gamma_out. This determined as
follows:
Gamma_out (Gamma_out_calculation.dsn):
The Gamma_out value is found as 0.315/-143.068. Hence the Gamma_L value is chosen as
0.315/143.068 to be conjugate matched.
11. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Ideal Circuit with Input Output Matching: (ideal_IO_matching_circuit.dsn)
a) Input matching circuit/Output Matching circuit:
Input Matching circuit:
Input matching network with respect to selected Гs value.
12. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Output matching circuit:
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RF-II CAD Project
We can see that first matching circuit works better. The return loss of this is almost equal to
Gamma_L. Thus Gamma_L and Gamma_out can be conjugately matched using this matching
circuit.
b) Biasing network:
The DC block and DC feed work very well to make sure RF signal follows the RF line path and
the DC current does not flow into the RF line path. Hence, the performance of the amplifier will
not be graded due to the biasing network. I directly went to the final design of the amplifier
using ideal elements and designed the biasing network similar to that in the lecture note slides.
c) Complete schematic: (ideal_IO_matching_circuit.dsn)
When the matching circuit was included I found the gain less than 12 dB. So I had to vary Ra
which in turn affects the stability. But since my amplifier was very stable I lost a little stability to
improve my gain. I increased the value of Ra from 1800 to 3000 to improve the gain. My
minimum gain in bandwidth was 12.7 dB which was well within (14 ± 1.5 dB)
Except gain I met all other specification very well
14. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
d) Simulated performance (ideal_IO_matching_circuit.dsn):
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RF-II CAD Project
From the graphs we can see that the amplifier meets all the design specifications. Next step was
to test the amplifier using parasitic models.
e)
Specification GOAL ACHIEVED GOAL MET OR
NOT
Fc (GHz) 1.9 1.9
% Bandwidth 20 20 Met
Gain (dB) 14 +/- 1.5 12.7 Met
NF max (dB) 2 1.784 Met
Input RL (dB) >12 17.9 Met
Output RL (dB) >20 35.45 Met
Stability Unconditional Unconditional Met
Zo (Ohms) 50 50
16. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Design using full parasitic models
Bias network:
The choice for the inductors and capacitors in the biasing network were done by
simulating each component individually and finding the value with a very large
reflection.
First let choose the value C,
So we can see that 7.2 pF works well. So I chose that.
Next we had to a pick values of inductor that we can use in the feed network.
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RF-II CAD Project
46 nH has a high reflection compared to other values. So it was chosen.
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RF-II CAD Project
Modelithic Model (full_modelithic_model.dsn):
Simulation Performance for Modelithic Model:
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RF-II CAD Project
Bottom:
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RF-II CAD Project
Left:
Right:
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RF-II CAD Project
Simulated performance:
25. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
From the above graphs it is seen that all the design parameters were achieved. After including
the matching networks, I found the my gain was degraded, where my min gain in bandwidth was
11.2 dB. I tried to vary all noise figure to parameters as I could. Firstly I change value of resistor
at output, but it didn’t improve my gain much. Then I changed my biased voltage from +3 V to
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RF-II CAD Project
+3.5 V, but it degraded my noise to +3. The gain did not match up to the required spec.The
transistor even after adding the matching circuit was unconditionally stable in the specified
frequency range.
The gain did not match up to the required spec.
Compliance Matrix:
Specification GOAL ACHIEVED GOAL MET OR
NOT
Fc (GHz) 1.9 1.9
% Bandwidth 20 20 Met
Gain (dB) 14 +/- 1.5 12.06 -
NF max (dB) 2 1.837 Met
Input RL (dB) >12 19.7 Met
Output RL (dB) >20 25.02 Met
Stability Unconditional Unconditional Met
Zo (Ohms) 50 50
27. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Physical layout for design:
The design I had made was selected because it met our specifications better. We had to generate
the layout in such a way that the components did not overlap.
Fabricated Design:
28. EEL 4422/EEL 6427 – RFII – Spring 2016, GM
RF-II CAD Project
Summary:
A low noise amplifier was designed meeting all the design specifications expect gain. The project
helped me to understand the theoretical concepts of gain circles noise, figure circles, input output
conjugate matching, tuning and optimization in ADS. The stability and biasing point of the
transistor. I learnt the importance making a transistor unconditionally stable and also the steps
needed to be taken for that. I also understood design tradeoffs required for design of amplifier and
parameters which can be varied and kept constant to reach the required specification. I made use
of the concept of resistive loading to make my transistor stable and also leant which part of the
circuit I needed to modify to improve the performance of the system. Then I got an insight as to
how parasitics affect a system at high frequencies. Replacing the Ideal DC block and feed by L
and C components help in avoiding the parasitic effect at high frequency. I also got know the
techniques to ensure the effect of parasitics on the system was minimum. Finally, I designed the
layout which could be used for fabrication. I understood the spacing I needed to give to avoid
overlapping of the components. Finally, I also had a chance to test the fabricated amplifier and
measure how the amplifier I designed is used for measurements.
