This document describes SysML-Companion, a tool that automatically generates simulatable and analyzable models from SysML specifications. It allows engineers to create a single SysML model as a common repository, then perform virtual prototyping and testing through simulation and hardware-in-the-loop testing. The document provides an example of using SysML-Companion to model and simulate a simple circuit containing both digital and analog components. Key benefits include enabling early testing, reducing prototype costs, and shortening time to market.