Unit 04

Department of Communication Engineering, NCTU 1
Unit 4 Application of Boolean
Algebra

Logic Design Unit 4 Application of Boolean Algebra Sau-Hsuan Wu
 Three main steps in designing a single-output
combinational logic circuit
 Find a switching function that specifies the desired
behavior of the circuit
 Find a simplified algebraic expression for the function
 Realized the simplified function using available logic
elements
 Goals:
 How to specify circuit behaviors
 How to design a combinational logic circuit

4.1 Conversion of English
Sentences to Boolean Equations

 For simple problems, go directly from a word description
of the desired circuit behavior to an algebra expression
 Mary watches TV if it is Monday night and she has
finished her homework.
F = A˙B
 The alarm will ring iff
the alarm switch is turned on
and the door is not closed,
or it is after 6 P.M.
and the window is not closed.
Z = AB' + CD'

4.2 Combinational Logic Design
Using a Truth Table

 In general, a truth table to design logic circuits
 First, list a true table
 E.g.
 Derive an algebraic expression for f from the table
f = A'BC + AB'C' + AB'C + ABC' + ABC (4-1)
= A+BC

 In stead of writing f in terms of the 1’s of the function,
we may also write f in terms of the 0’s of the function
 E.g.
f ' = (A+B+C)(A+B+C')(A+B'+C) (4-3)
= (A+B)(A+B'+C) = A + BC

4.3 Minterm and Maxterm
Expansions

 Each term in (4-1) is referred to as a minterm
 f = A'BC + AB'C' + AB'C + ABC' + ABC (4-1)
 A function written as a sum of minterms is referred to
as a minterm expansion or a standard SOP
 Each term in (4-3) is referred to as a maxterm
 f = (A+B+C)(A+B+C')(A+B'+C) (4-3)
 A function written as a product of maxterms is referred
to as a maxterm expansion or a standard POS

 A minterm of n variables is a product of n literals in
which each variable appears exactly once in either true or
complemented form
 The decimal notation of minterm expansion
e.g. f = m (3,4,7)

 A maxterm of n variables is a sum of n literals in which
each variable appears exactly once in either true or
complemented form
 The decimal notation of maxterm expansion
E.g. f = M(0,,2)
 Given the minterm or maxterm expansions for f , the
minterm or maxterm expansions for the complement of f
are easy to obtain
 E.g.
 Or
0 1 2
3 4 5 6 7
(0,1,2)
(3,4,5,6,7)
f m m m m
f M M M M M M
   
 


0 1 2 0 1 2 0 1 2( )f M M M M M M m m m      

 A general switching expansion can be converted to
minterm or maxterm expansion either using a truth table
or algebraically
 For algebraic method, first write the expansion as a sum
of products and then introduce the missing variables in
each term by applying the theorem X + X’=1
 Example f(a,b,c,d) = a’(b’+d) + acd’
 1> SOP: f= a’b’+a’d+acd’
 Introduce missing variables
f= a’b’(c+c’)(d+d’)+a’(b+b’)(c+c’)d’+ a(b+b’)cd’
= a’b’c’d’+a’b’c’d+a’b’cd’+a’b’cd+a’b’c’d+a’b’cd
+ a’b’cd + a’bcd + abcd’+ ab’cd’
= m (0,1,2,3,5,7,10,14)

 General minterm and maxterm expansions
 A general minterm expansion
f = a0m0 + a1m1+  + a7m7 = ai mi
ai = 0 or 1
 mi is not present if ai = 0
 A general maxterm expansion
f = (a0 + m0)(a1 + m1)  (a7 + m7) = (ai + mi)
ai = 0 or 1
 mi is not present if ai = 1
 Equality ai mi = (ai + mi)

4.5 Incompletely Specified
Functions

 A large system is usually divided into many subcircuits.
The output of module 1 may not generate all possible
combinations for the input variables of module 2.
 In this case, we don’t care these specific combinations
when designing the switch circuit for B

 When realizing the function, the don‘t care terms can be
assigned 0’s or 1’s
 If both X’s are assigned 0
F = A'B'C' + A'BC +ABC = A'B'C' + BC
 If first X is assigned 1 and the second 0
F = A'B'C' + A'B'C + A'BC +ABC = A'B' + BC
 If we assign 1 to both X’s
F = A'B'C' + A'B'C + A'BC + ABC' + ABC
= A'B' + BC + AB

4.5 Examples of Truth Table
Construction

 Error detector for 6-3-1-1 binary-coded-decimal digits

 Switching Expression


4.5 Design of Binary Adders

 Design a 4-bit binary ripple carry adder
 Approach 1:
construct a truth table
 Approach 2: cascade 4 1-bit Full Adders

 Construct the true table for
1-bit full adder
 Find the switching expressions
( ) ( )
( ) ( )
in in in in
in in in in
in in in
Sum X Y C X YC XY C XYC
X Y C YC X Y C YC
X Y C X Y C X Y C
      
      
       
( ) ( ) ( )
out in in in in
in in in in in in
in in
C X YC XY C XYC XYC
X YC XYC XY C XYC XYC XYC
YC XC XY
     
       
  

 Implement the functions with logic gates
 Overflow occurs if adding two positive numbers gives a
negative result, or adding two negative numbers results in
a positive number
3 3 3 3 3 3V A B S A B S    

 The pros and cons of ripple carry adder
 Simple in concept
 The carry output at stage i+1
Ci+1 = XiYi + (Xi + Yi) Ci
 The carries propagate like a ripple and introduce circuit
delays : C0 C1  C2   Ci+1
 Ci+1 = f (Xi,Yi, Ci) = f (Xi,Yi,Xi-1,Yi-1,Ci-1) = 
 Alternative: Carry lookahead adder
 To avoid circuit delays due to the propagation of
carries
 Express Ci+1 in terms of C0 and {X0,Yi  Xi,Yi} only

 Re-write the output carry at the ith stage as
 Ci+1 = gi + pi Ci
 The carry-generate function: gi = XiYi
 The carry-propagate function pi = Xi + Yi
 Expression the carry bit in terms of gi and pi
 C1 = g0 + p0 C0
 C2 = g1 + p1 C1 = g1 + p1 g0 + p1 p0 C0
 C3 = g2 + p2 C2 = g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 C0
 
 Ci = gi + pi gi-1 + pi pi-1gi-2 +  + pi pi-1 pi-2  g0
+ pi pi-1 pi-2  p0C0

 The circuit implementation of 4-bit carry lookahead adder
block
Carry lookahead network

 For adders with higher number of bits, the carry
lookahead network can get quite large in terms of gates
and gate inputs. This also presents a limitation in the
realization of a large high speed adder
 How to circumvent this problem?
 Cascade 4-bit carry lookahead adders to form a lager adder

 Partition the operands into blocks
E.g.
C8 = g7 + p7 g6 + p7 p6g5 + p7 p6p5g4 + p7 p6p5p4g3 +
p7 p6p5p4p3g2 + p7 p6p5p4p3p2g1 + p7 p6p5p4p3p2p1g0+
p7 p6p5p4p3p2p1p0C0
= g7 + p7 g6 + p7 p6g5 + p7 p6p5g4 +
p7 p6p5p4 (g3 + p3g2 + p3p2g1 + p3p2p1g0) +
p7 p6p5p4(p3p2p1p0C0)
= G1 + P1G0 + P1P0C0
G1= g7 + p7 g6 + p7 p6g5 + p7 p6p5g4
P1 = p7 p6p5p4
G0= g3 + p3g2 + p3p2g1 + p3p2p1g0
P0 = p3p2p1p0

 Define a 4-bit carry lookahead generator as
G= g3 + p3g2 + p3p2g1 + p3p2p1g0
P = p3p2p1p0

Unit 04

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