The presentation covers, Field Effect Transistor: Construction and Characteristic of JFETs, dc biasing of CS, ac analysis of CS amplifier, MOSFET (Depletion and Enhancement)Type, Transfer Characteristic

1. Field Effect Transistor
Unit II
Bipolar Junction Transistor: Transistor Construction, Operation, Amplification action.
Common Base, Common Emitter, Common Collector Configuration DC Biasing BJTs: Operating
Point, Fixed-Bias, Emitter Bias, Voltage-Divider Bias Configuration. Collector Feedback,
Emitter-Follower Configuration. Bias Stabilization. CE, CB, CC amplifiers and AC analysis of
single stage CE amplifier (re Model ). Field Effect Transistor: Construction and Characteristic
of JFETs. AC analysis of CS amplifier, MOSFET (Depletion and Enhancement)Type, Transfer
Characteristic
11/6/2017 1
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad

2. Field Effect Transistor (FET)
11/6/2017 2
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
BJT
Base B
Collector C
Emitter E
Control
Current IB
IC
FETGate G
Drain D
Source S
Control
Voltage VGS
ID
Current Controlled device BJT Voltage Controlled device FET
• BJT is current-controlled, whereas FET is voltage-controlled device
• BJT is bipolar device (electrons and holes contribute in currents)
whereas FET is a unipolar device; current conducts either due to
electron (n-channel) or hole (p-channel).

3. Field Effect Transistor (FET)
• In FET an electric field, due to biasing voltage, controls the current
conduction path of device, hence the name Field effect transistor
• FET have high input impedance than BJT
• FET are more temperature stable than BJT
• FETs are of two types:
– junction field-effect transistor (JFET), and
– metal–oxide–semiconductor field-effect transistor (MOSFET),
MOSFET are of two types;
• depletion and
• enhancement
11/6/2017 3
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad

4. Junction Field Effect Transistor (JFET): Construction
11/6/2017 4
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
• With no bias, the JFET has two p–n junctions
resulting in depletion region at each junction
n-channel JFET construction
n
pp
Source S
Drain D
Gate G
Ohmic contacts
Depletion
region
S
G +
-
ID
D +
VDS
-VGS S
G +
-
ID
D +
VDS
-VGS
n-channel JFET symbol p-channel JFET symbol
• n-type material connected to drain (D) and source (S), forms the
channel between the p-material layers.
• The two p materials are connected to gate (G) terminal

5. Junction Field Effect Transistor (JFET): Working
11/6/2017 5
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
VGS=0 and VDS>0
• When VGS=0 & VDS is +ve, a decreasing reverse bias
potential is applied across p-n junction from drain
to source, resulting in wide depletion at drain end
which goes on reducing towards source
• Due to VDS, current flows. Drain and source
currents are equal (ID=IS).
• charge flow is uninhibited and is limited by
resistance of n-channel between drain and source.
• Due to reverse bias p-n junction, gate current IG 0,
which is an important characteristic of the JFET
Varying reverse bias
potential at p-n junction
S
D
G
2 V
0 V
1.5 V
1.0 V
0.5 V
n
p p
n-channel JFET at VGS=0
S
D
G
Depletion
region +
VDS
-
+
VGS=0
-
n
p p

6. Junction Field Effect Transistor (JFET): Working
11/6/2017 6
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
VGS=0 and pinch off voltage
• With Initial increase of VDS from 0, ID increase
linearly (constant channel resistance)
• Further increase of VDS results in channel width
reduction due to depletion widening, causing
slowdown in increase of ID.
• As VDS=VP (pinch off voltage), it appears that
two depletion regions ‘touch’ each other and ID
is saturated to IDSS (a very small channel exist and a
very high density current flows)
• When VDS>VP, the region of ‘touching’ depletion
increases in length & ID remains saturated. JFET
behaves as constant current source
n-channel JFET at
VGS=0 & VDS=VP
S
D
G
Depletion
region +
-
+
VGS=0
-
n
p p
VDS =VP
Output characteristics
of JFET at VGS=0
VDS
ID
IDSS
VP
VGS =0
Increasing resistance due
to narrowing channel

7. JFET Characteristics
11/6/2017 7
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
VGS<0 and VDS>0
• -ve VGS results in similar curve with
reduced VP & saturation current.
• pinch-off voltage drop in parabolic
manner as VGS goes more negative.
• At VGS= -VP , JFET will be ‘off’ (ID=0)
• For VDS> VDS max , breakdown occurs
• VP is +ve for for p-channel JFET. VP is also referred as VGS(off)
• Saturation is also called constant current / linear amplification region
• JFET behaves as variable resistor in ohmic region (controlled by VGS)
Output characteristics of n-channel JFET
VDS
ID
IDSS
VGS =0
VGS =-1 V
VGS =-2 V
VGS =-3 V
VGS =-4 V= -VP
Locus of pinch off values
Saturation region
Ohmic
region
VP for VGS=0
8
7
6
5
4
3
2
1
0 5 10 15 20 25
Breakdown
region
VDS max

8. JFET Characteristics Transfer curve
11/6/2017 8
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
Output characteristics of n-channel JFET
VDS
ID(mA)
IDSS VGS =0
VGS =-1 V
VGS =-2 V
VGS =-3 V
VGS =-4 V= VP
VP for VGS=0
8
7
6
5
4
3
2
1
0
5 10 15 20 25
Breakdown
region
VDS max
-4 -3 -2 -1
8
7
6
5
4
3
2
1
0
VGS
ID(mA)
Transfer characteristics
of n-channel JFET
Transfer characteristics of JFET is given by Shockley’s equation
2
1 






P
GS
DSSD
V
V
II

9. Depletion MOSFET, Transfer Characteristic
• MOSFET is Metal Oxide Semiconductor Field Effect Transistor and are
of two types; depletion and enhancement type
• It does not have p-n junction structure as in JFET
• SiO2 layer (dielectric insulator) isolates gate and channel.
• SiO2 layer results in very high input impedance
11/6/2017 9
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
n-channel D-MOSFET symbol p-channel D-MOSFET symbol
S
G
+
-
ID
D +
VDS
-VGS S
G
+
-
ID
D +
VDS
-VGS
n-channel D-MOSFET construction
P
substrate
Gate G
SiO2 layer
n
n
Source S
Drain D
n-channel

10. D-MOSFET, Operation & Transfer Characteristic
11/6/2017 10
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
For n channel D-MOSFET, with VDS>0
• At VGS=0, current ID flows through the channel.
The current is labelled as IDSS
• With VGS<0, channel depletes & current ID
reduces with increasing -ve bias.
• at VGS=VP (pinch off voltage; a –ve voltage),
channel fully depletes & current ID=0
• With +ve VGS, channel enhances & ID increases
S
G
+
-
ID
D
+
VDS
-VGSVGG
VDD
n-channel D-MOSFET
• Shockley’s equation of JFET is applicable for the D-MOSFET
on the drain or transfer characteristics
• region of +ve gate voltage is referred as enhancement region
• region with VP< VGS<0 is referred as depletion region
• region with VGS< VP is referred as cut off region

11. D-MOSFET, Operation & Transfer Characteristic
11/6/2017 11
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
Transfer characteristics
of n-channel D-MOSFET Output (Drain) characteristics of n-channel D-MOSFET
VDS
ID(mA)
IDSS
VGS =0
VGS =-1 V
VGS =-2 V
VGS =-3 V
VGS =-4 V= VP
VP for VGS=0
8
7
6
5
4
3
2
1
0 5 10 15 20 25-4 -3 -2 -1
8
7
6
5
4
3
2
1
0VGS
ID(mA) VGS =1 V
-VP
Depletion
mode Enhancement mode
Transfer characteristics of D-MOSFET is given by Shockley’s equation
2
1 






P
GS
DSSD
V
V
II

12. Enhancement MOSFET, Transfer Characteristic
• E-MOSFET has no structured channel
• Gate voltage induces a channel by by creating a thin layer of charge
carriers in the substrate near the gate.
• +ve VGS, results in n-channel by while -ve VGS, results in p channel
• conductivity of channel is enhanced by increasing the VGS
• SiO2 layer accounts for the very high input impedance.
11/6/2017 12
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
n-channel D-MOSFET symbol p-channel D-MOSFET symbol
S
G
+
-
ID
D +
VDS
-VGS
S
G
+
-
ID
D +
VDS
-VGS
P
substrate
n-channel D-MOSFET construction
Gate
G
SiO2 layer
n
nSource S
Drain D

13. E-MOSFET, Operation & Transfer Characteristic
11/6/2017 13
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
For n channel E-MOSFET, with VDS>0
• when 0<VGS<VT (threshold voltage) current
ID is zero due to absence of channel
• With VGSVT, electrons of p-substrate
induces a channel for drain current flow.
• with VGSVT with increase in VDS, ID
saturates due to pinching-off (narrower
channel at drain end of induced channel )
S
G
+
-
ID
D
+
VDS
-VGSVGG
VDD
n-channel E-MOSFET
on the drain or transfer characteristics
• region of +ve gate voltage is referred as
enhancement region
• region with VGS< VT is referred as cut off region
P
substrate
Pinching off in n-channel
E-MOSFET with VGS>VT & VDS>0
Gate
G
SiO2 layer
n
nSource S
Drain D

14. E-MOSFET, Transfer Characteristic
11/6/2017 14
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
Transfer characteristics
of n-channel E-MOSFET Output (Drain) characteristics of n-channel E-MOSFET
VDS
ID(mA)
IDSS VGS =0
VGS =-1 V
VGS =-2 V
VGS =-3 V VGS= VT= 2 V
10
9
8
7
6
5
4
3
2
1
0 5 10 15 20 252 3 4 5 6 7 VGS
ID(mA) VGS =1 V
VT
10
9
8
7
6
5
4
3
2
1
0
For VGS>VT  
deviceofonconstructioffunctionisandconstantis
2
k
VVkI TGSD 

15. FET: DC Biasing Operating Point
•ac power increase (amplification) is due to energy transfer by dc bias
•both dc & ac response is required for analysis/design of FET amplifier
•To find Q point (operating point), output voltage & output current due
to dc biasing has to be known. (for CS configuration, ID , VDS and VGS )
11/6/2017 15
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
and0 SDG III 
•Each configuration is analysed by recurring use of following equations
2
1MOSFET-D&JFETfor 






P
GS
DSSD
V
V
II  2
1MOSFET-Efor TD VkI 
•ac power increase (amplification) is due to energy transfer by dc bias
•both dc & ac response is required for analysis/design of FET amplifier
•To find Q point (operating point), output voltage & output current due
to dc biasing has to be known. (for CS configuration, ID , VDS and VGS )

16. FET: Voltage-Divider Bias
11/6/2017 16
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
calculatedisandequation,twotheSolving
1
and
,0as
2
21
2
21
2
GSD
P
GS
DSSD
SD
DD
GS
SDGGS
DD
G
SDG
VI
V
V
II
RI
RR
VR
V
RIVV
RR
VR
V
III














Voltage divider bias
VDD
ID
RDR1
+
-
Input ac
signal
Output
ac signal
C1
C2
VDS
IS
RS
R2
I1
I1
S
G
D
VGS
 SDDDDDS RRIVV 

17. FET: Voltage-Divider Bias Example
11/6/2017 17
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
 
 
 
mA66.6IandV71.1so
holdnotdoeswhichVV&0I,Vifas
V71.1V,7.4getwesolving
003.841.6or
69971.0409.0or
3004.061037.2ngsubstitution
3004.0
3
V
1120.0I&61037.2
V37.220
93
11
,,0as
D
GSGDP
2
2
2
2
2
GS
D
21
2

















GS
GS
GS
GSGS
GSGSGS
GSGS
GSDGS
DD
GSDG
V
V
V
VV
VVV
VxV
VIV
x
RR
VR
VIII
V62.261.266.620  xVDS
R2=
11 M
RD=
2 K
RS=
610 
Voltage divider bias
VDD=20 V
ID
R1=
82 M
+
-C1
C2
IS
I1
I1
S
G
D
VGS
IDSS =12 mA
VP = -3 V
rd =100 K

18. AC analysis of CS amplifier
11/6/2017 18
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
• FET amplifiers give excellent voltage gain with high input
impedance, low power consumption, and high frequency range
• Transconductance gm of FET is given as
P
DSSD
P
GS
P
DSS
GS
D
m
V
II
V
V
V
I
V
I
g
2
1
2










GSVD
DS
d
I
V
r
constant
FET,ofimpedenceoutput



To make ac equivalent model
• replace dc supplies by zero (short circuit)
• replace coupling /bypass capacitor by short
circuit
• Remove elements bypassed by short circuit
• define the parameters Zi, ZO, Av, and VO
+
-
G
S
D
S
VGS rd
JFET ac equivalent circuit
gmVGS

19. FET: ac analysis of CS amplifier
11/6/2017 19
REC 101 Unit II by Dr Naim R Kidwai,
Professor & Dean, JIT Jahangirabad
 




i
O
i
Ddm
i
O
V
DdO
i
I
I
A
Rrg
V
V
A
RrZ
RRZ
gainCurrent
gainVoltage
21
+
-
VGS rd
ac equivalent circuit
gmVGS
VDD
Voltage divider bias CS amplifier
ID
RDR1
C1 C2
RS
R2
S
G
D
+
Vi
-
+
VO
-
ac equivalent
ID
RDR1
+
-
R2
S
G
D
VGS
+
Vi
-
+
VO
-
R2
R1 RD
CS
+
-
Vi
+
-
VO