1. Serial Peripheral Interface (SPI)Serial Peripheral Interface (SPI)
Master CoreVerificationMaster CoreVerification
By: Maulik Suthar

2. IntroductionIntroduction
What is SPI?
Properties of SPI
SPI Master Core Specification
Verification Approach
Environment Diagram
Testcases
BUGS!!
Conclusion

3. What is SPI?What is SPI?
SPI stands for Serial Peripheral Interface.
Synchronous Serial Bus protocol
developed by Motorola.
Also known as SSI(Synchronous Serial
Interface)
4-wired serial bus.
Simple, fast, easy to use.
Accepted by wide number of devices
offering serial data transmission.

4. Properties of SPIProperties of SPI
Always FULL DUPLEX.
Devices communicate in master-
slave mode, master initiates the transfer.
Single master – multiple Slaves
Single slave is active at a given instance of
time.
Variable transmission speed from slave
supported.

5. INTERFACEINTERFACE
The SPI bus specifies four logic signals
SCLK: serial clock (output from master)
MOSI: master output, slave input
MISO: master input, slave output
SS: slave select (slave enable signal,
output from master)

6. Data TransmissionData Transmission
Host configures the master
Master initiates the transfer by selecting
the slave, and starting the SCLK.
Data from master shifts out from MOSI
and slave data shifts in via MISO

7. SPI Master Core ArchitectureSPI Master Core Architecture

8. FeaturesFeatures
Full duplex synchronous serial data transfer
Variable length of transfer word up to 128 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial
clock independently
8 slave select lines
Fully static synchronous design with one clock
domain
Technology independent Verilog
Fully synthesizable

9. Wishbone InterfaceWishbone Interface
 SPI Master acts as a slave to the Wishbone Interface.
 Wishbone communicates with the host
 Bus signals are as described below:

10. SPI Core registersSPI Core registers
Data receive registers, Data transmit register
◦ Both are same registers, total four registers each of 32 bits
◦ Received data is stored in Rx0, Rx1, Rx2, Rx3 after read
cycle
◦ Transmitted data is stored in Tx0, Tx1, Tx2, Tx3 during
write cycle
Divider register
◦ This register specifies the SCLK frequency which is derived
by dividing the Master clock

11. Registers Contd.Registers Contd.
Slave Select register
◦ bits [7:0] defines the current active slave out of 8
slaves.
◦ It employs 1-hot encoding as to enable only 1 slave at
a time, it its automatically set by master if ASS bit in
CTRL is set to 1.
Control and status register

12. Verification approachVerification approach
Master agent is established to simulate the
wishbone protocol signals from host side.
Slave agent is established to simulate the SPI
protocol.
Each agent has its individual sequencer, monitor
and driver.
The virtual sequencer and scoreboard are
included in the environment and the top level
module which encapsulates the RTL along with
the Testcases.

14. Steps to drive the DUVSteps to drive the DUV
 To drive the DUV we need to make the signals
wb_we_i = 1,
wb_stb_i = 1,
wb_cyc_i = 1.
 This will activate the SPI Master Core and indicate a
valid write cycle.
 Supply the address of the SPI core registers to write
into and wait for the ack to arrive from the core.
 After configuring the data, divider, and ss registers at
last configure the CTRL register by making GO_BUSY
bit to 1 and start the slave data transfer.

15. Contd.Contd.
After slave completes writing the data
into core’s data registers wb_int_o signal
will be asserted.
This indicates end of a valid bus cycle and
core is ready to proceed for next cycle.

16. TestcasesTestcases
Test_1
◦ LSB =1, TxNEG = 1, RxNEG = 0.
Test_2
LSB =1, TxNEG = 0, RxNEG = 1.
Test_3
LSB =0, TxNEG = 0, RxNEG = 1.
Test_4
LSB =0, TxNEG = 1, RxNEG = 0.

17. BUGS!!BUGS!!
Able to find two BUGS!! In the design of
SPI master core.
First bug is found in MISO coming from
slave side.
When the SCLK starts, the data to be
transferred is not arriving at triggering
edge of the SCLK as a result X is
transferred into the master.

18. Screenshot of BUGScreenshot of BUG

19. Another BUG!! Is found in the MOSI
coming out of the master core.
The applied data to be transmitted to
slave is shifted 1-bit right, when collected
from slave monitor.
01001001110111010101100011000100 MOSI from master
monitor
00100100111011101010110001100010 MOSI from slave
monitor

20. Design with Multiple SlavesDesign with Multiple Slaves
• Design with a single master and multiple
independent slaves.
• This Design supports up to 8 slaves which can be
addressed using SS signal independently.

21. ConclusionConclusion
Design was verified based on UVM
methodology.
Simulation was done in Questasim using
SystemVerilog.
Two critical bugs were found during
Verification.
Functional coverage was implemented
and achieved 92.85% of functional code
coverage for this design.

22. Pros & Cons of SPIPros & Cons of SPI
Fast & easy to implement.
Best choice for point-to-point
connections.
Easily supported by devices.
Lack of ACK mechanism.
Doesn't have in-built addressing for
slaves
Multiple slaves increases its complexity.
No data error control and flow control.
Cant detect if slave present or not.