FET POWER & DELAY/FREQUENCY TECHNIQUES

POWER & DELAY/FREQUENCY
IN A FET

Contents
• Introduction
• Dynamic power
• Short circuit power
• Reduced supply voltage operation
• Glitch elimination
• Static (leakage) power reduction
• Low power systems
• State encoding
• Processor and multi-core design
Bijoy Goswami , Dept. of ETE, AEC

Introduction
Why is it a concern?
Business & technical needs
Semiconductor processing technology
Power Consumption of VLSI Chips

NEED FOR LOW POWER
• More transistors are packed into the chip.
• Increased market demand for portable devices.
• Environmental concerns

Meaning of Low-Power Design
• General considerations in low-power design
• Algorithms and architectures
• High-level and software techniques
• Gate and circuit-level methods
• Power estimation techniques
• Test power

•What is the Power Consumption in MOSFET?

Leakage Power
IG
ID
Isub
IPT
IGIDL
n+ n+
Ground
VDD
R

• Total Power = Pswitching + Pshort-circuit + Pleakage
• Dynamic power is the sum of two factors: switching power plus short-circuit power.
• Switching power is dissipated when charging or discharging internal and net
capacitances.
• Short-circuit power is the power dissipated by an instantaneous short-circuit connection
between the supply voltage and the ground at the time the gate switches state.
• Pswitching = a.f.Ceff.Vdd2
Where a = switching activity, f = switching frequency, Ceff = the effective capacitance and
Vdd = the supply voltage.

• Pshort-circuit = Isc.Vdd.f
• Where Isc = the short-circuit current during switching, Vdd = the supply voltage and f
= switching frequency.
• Dynamic power can be lowered by reducing switching activity and clock frequency,
which affects performance; and also by reducing capacitance and supply voltage.
Dynamic power can also be reduced by cell selection-faster slew cells consume less
dynamic power.
• Leakage power is a function of the supply voltage Vdd, the switching threshold
voltage Vth, and the transistor size.
• PLeakage = f (Vdd, Vth, W/L)
• Where Vdd = the supply voltage, Vth = the threshold voltage, W = the transistor width
and L = the transistor length.

Issues with Scaling and Moor’s law:

•Nonideal Transistor Behavior
• High Field Effects
• Mobility Degradation
• Velocity Saturation
• Channel Length Modulation
• Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
• Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage
• Process and Environmental Variations

Ideal Transistor I-V
• Shockley long-channel transistor models
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V



 

  
= − − 
 

 


− 



Ideal vs. Simulated nMOS I-V Plot
• 65 nm IBM process, VDD = 1.0 V
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
1200
Vds
Ids (A)
Vgs = 1.0
Vgs = 1.0
Vgs = 0.8
Vgs = 0.6
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Channel length modulation:
Saturation current increases
with Vds
Ion = 747 mA @
Vgs = Vds = VDD
Simulated
Ideal
Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with Vgs
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

ON and OFF Current
• Ion = Ids @ Vgs = Vds = VDD
• Saturation
• Ioff = Ids @ Vgs = 0, Vds = VDD
• Cutoff
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
Vds
Ids (A)
Vgs = 1.0
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Ion = 747 mA @
Vgs = Vds = VDD

Mobility Degradation (Surface Scattering) and Velocity
Saturation:

a-Power Model
0 cutoff
linear
saturation
gs t
ds
ds dsat ds dsat
dsat
dsat ds dsat
V V
V
I I V V
V
I V V
 


= 


 

( )
( )
/ 2
2
dsat c gs t
dsat v gs t
I P V V
V P V V
a
a

= −
= −

Channel Length Modulation
• Reverse-biased p-n junctions form a depletion region
• Region between n and p with no carriers
• Width of depletion Ld region grows with reverse bias
• Leff = L – Ld
• Shorter Leff gives more current
• Ids increases with Vds
• Even in saturation
n
+
p
Gate
Source Drain
bulk Si
n
+
VDD
GND VDD
GND
L
Leff
Depletion Region
Width: Ld

Chan Length Mod I-V
• l = channel length modulation coefficient
• not feature size
• Empirically fit to I-V characteristics
( ) ( )
2
1
2
ds gs t ds
I V V V

l
= − +

Threshold Voltage Effects
• Vt is Vgs for which the channel starts to invert
• Ideal models assumed Vt is constant
• Really depends (weakly) on almost everything else:
• Body voltage: Body Effect
• Drain voltage: Drain-Induced Barrier Lowering
• Channel length: Short Channel Effect

Body Effect
• Body is a fourth transistor terminal
• Vsb affects the charge required to invert the channel
• Increasing Vs or decreasing Vb increases Vt
• fs = surface potential at threshold
• Depends on doping level NA
• And intrinsic carrier concentration ni
• g = body effect coefficient
( )
0
t t s sb s
V V V
g f f
= + + −
2 ln A
s T
i
N
v
n
f =
si
ox
si
ox ox
2q
2q A
A
N
t
N
C

g 

= =

Body Effect Cont.
• For small source-to-body voltage, treat as linear

DIBL
• Electric field from drain affects channel
• More pronounced in small transistors where the drain is closer to the
channel
• Drain-Induced Barrier Lowering
• Drain voltage also affect Vt
• High drain voltage causes current to increase.
ttdsVVV=−
t t ds
V V V

 = −

Short Channel Effect
• In small transistors, source/drain depletion regions extend into the
channel
• Impacts the amount of charge required to invert the channel
• And thus makes Vt a function of channel length
• Short channel effect: Vt increases with L
• Some processes exhibit a reverse short channel effect in which Vt decreases
with L

Leakage
• What about current in cutoff?
• Simulated results
• What differs?
• Current doesn’t
go to 0 in cutoff

Leakage Sources
• Subthreshold conduction
• Transistors can’t abruptly turn ON or OFF
• Dominant source in contemporary transistors
• Gate leakage
• Tunneling through ultrathin gate dielectric
• Junction leakage
• Reverse-biased PN junction diode current

Subthreshold Leakage
• Subthreshold leakage exponential with Vgs
• n is process dependent
• typically 1.3-1.7
• Rewrite relative to Ioff on log scale
• S ≈ 100 mV/decade @ room temperature
0
0e 1 e
gs t ds sb ds
T T
V V V k V V
nv v
ds ds
I I
g

− + − −
 
= −
 
 
 

Gate Leakage
• Carriers tunnel thorough very thin gate oxides
• Exponentially sensitive to tox and VDD
• A and B are tech constants
• Greater for electrons
• So nMOS gates leak more
• Negligible for older processes (tox > 20 Å)
• Critically important at 65 nm and below (tox ≈ 10.5 Å)
From [Song01]

Junction Leakage
• Reverse-biased p-n junctions have some leakage
• Ordinary diode leakage
• Band-to-band tunneling (BTBT)
• Gate-induced drain leakage (GIDL)
n well
n+
n+ n+
p+
p+
p+
p substrate

Gate Tunneling:

Diode Leakage
• Reverse-biased p-n junctions have some leakage
• At any significant negative diode voltage, ID = -Is
• Is depends on doping levels
• And area and perimeter of diffusion regions
• Typically < 1 fA/m2 (negligible)
e 1
D
T
V
v
D S
I I
 
= −
 
 
 

Band-to-Band Tunneling
• Tunneling across heavily doped p-n junctions
• Especially sidewall between drain & channel
when halo doping is used to increase Vt
• Increases junction leakage to significant levels
• Xj: sidewall junction depth
• Eg: bandgap voltage
• A, B: tech constants

Gate-Induced Drain Leakage
• Occurs at overlap between gate and drain
• Most pronounced when drain is at VDD, gate is at a negative voltage
• Thwarts efforts to reduce subthreshold leakage using a negative gate voltage

Temperature Sensitivity
• Increasing temperature
• Reduces mobility
• Reduces Vt
• ION decreases with temperature
• IOFF increases with temperature
Vgs
ds
I
increasing
temperature

Impact Ionization

Hot carrier effect:

Parameter Variation
• Transistors have uncertainty in parameters
• Process: Leff, Vt, tox of nMOS and pMOS
• Vary around typical (T) values
• Fast (F)
• Leff: short
• Vt: low
• tox: thin
• Slow (S): opposite
• Not all parameters are independent
for nMOS and pMOS
nMOS
pMOS
fast
slow
slow
fast
TT
FF
SS
FS
SF

Environmental Variation
• VDD and T also vary in time and space
• Fast:
• VDD: high
• T: low

Process Corners
• Process corners describe worst case variations
• If a design works in all corners, it will probably work for any variation.
• Describe corner with four letters (T, F, S)
• nMOS speed
• pMOS speed
• Voltage
• Temperature

Multi gate MOSFET

DELAY/FREQUENCY ESTIMATION

Delay Definitions
• tpdr: rising propagation delay
• From input to rising output crossing VDD/2
• tpdf: falling propagation delay
• From input to falling output crossing VDD/2
• tpd: average propagation delay
• tpd = (tpdr + tpdf)/2
• tr: rise time
• From output crossing 0.2 VDD to 0.8 VDD
• tf: fall time
• From output crossing 0.8 VDD to 0.2 VDD

Delay Definitions
•tcdr: rising contamination delay
• From input to rising output crossing VDD/2
•tcdf: falling contamination delay
• From input to falling output crossing VDD/2
•tcd: average contamination delay
• tpd = (tcdr + tcdf)/2

Delay Estimation
• We would like to be able to easily estimate delay
• Not as accurate as simulation
• But easier to ask “What if?”
• The step response usually looks like a 1st order RC response with a
decaying exponential.
• Use RC delay models to estimate delay
• C = total capacitance on output node
• Use effective resistance R
• So that tpd = RC
• Characterize transistors by finding their effective R
• Depends on average current as gate switches

Effective Resistance
• Shockley models have limited value
• Not accurate enough for modern transistors
• Too complicated for much hand analysis
• Simplification: treat transistor as resistor
• Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
• R averaged across switching of digital gate
• Too inaccurate to predict current at any given time
• But good enough to predict RC delay

RC Delay Model
• Use equivalent circuits for MOS transistors
• Ideal switch + capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width
k
g
s
d
g
s
d
kC
kC
kC
R/k
k
g
s
d
g
s
d
kC
kC
kC
2R/k

RC Values
• Capacitance
• C = Cg = Cs = Cd = 2 fF/m of gate width in 0.6 m
• Gradually decline to 1 fF/m in 65 nm
• Resistance
• R  10 KW•m in 0.6 m process
• Improves with shorter channel lengths
• 1.25 KW•m in 65 nm process
• Unit transistors
• May refer to minimum contacted device (4/2 l)
• Or maybe 1 m wide device
• Doesn’t matter as long as you are consistent

Inverter Delay Estimate
• Estimate the delay of a fanout-of-1 inverter
C
C
R
2C
2C
R
2
1
A
Y
C
2C
C
2C
C
2C
R
Y
2
1
d = 6RC

Example: 3-input NAND
• Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).
3
3
3
2 2 2

3-input NAND Caps
• Annotate the 3-input NAND gate with gate and diffusion capacitance.
2 2 2
3
3
3
3C
3C
3C
3C
2C
2C
2C
2C
2C
2C
3C
3C
3C
2C 2C 2C
2 2 2
3
3
3
2 2 2
3
3
3
3C
3C
5C
5C
5C
9C

Elmore Delay
• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder
R1
R2
R3
RN
C1
C2
C3
CN
( ) ( )
nodes
1 1 1 2 2 1 2
... ...
pd i to source i
i
N N
t R C
R C R R C R R R C
− −

= + + + + + + +


Example: 3-input NAND
• Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates.
9C
3C
3C
3
3
3
2
2
2
5hC
Y
n2
n1
( )( ) ( )( ) ( ) ( )
( )
3 3 3 3 3 3
3 3 9 5
12 5
R R R R R R
pdf
t C C h C
h RC
= + + + + + +
 
 
= +
h copies
( )
9 5
pdr
t h RC
= +

Delay Components
•Delay has two parts
•Parasitic delay
• 9 or 12 RC
• Independent of load
•Effort delay
• 5h RC
• Proportional to load capacitance

Contamination Delay
• Best-case (contamination) delay can be substantially less than propagation delay.
• Ex: If all three inputs fall simultaneously
9C
3C
3C
3
3
3
2
2
2
5hC
Y
n2
n1
( )
5
9 5 3
3 3
cdr
R
t h C h RC
   
= + = +
    
 
   

Diffusion Capacitance
• We assumed contacted diffusion on every s / d.
• Good layout minimizes diffusion area
• Ex: NAND3 layout shares one diffusion contact
• Reduces output capacitance by 2C
• Merged uncontacted diffusion might help too
7C
3C
3C
3
3
3
2
2
2
3C
2C
2C
3C
3C
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
Shared
Contacted
Diffusion

Delay in a Logic Gate
• Express delays in process-independent unit
• Delay has two components: d = f + p
• f: effort delay = gh (a.k.a. stage effort)
• Again has two components
• g: logical effort
• Measures relative ability of gate to deliver current
• g  1 for inverter
• h: electrical effort = Cout / Cin
• Ratio of output to input capacitance
• Sometimes called fanout
• p: parasitic delay
• Represents delay of gate driving no load
• Set by internal parasitic capacitance
abs
d
d

=
 = 3RC
 3 ps in 65 nm process
60 ps in 0.6 m process

Delay Plots
d = f + p
= gh + p
• What about
NOR2?
Electrical Effort:
h = Cout / Cin
Normalized
Delay:
d
Inverter
2-input
NAND
g = 1
p = 1
d = h + 1
g = 4/3
p = 2
d = (4/3)h + 2
Effort Delay: f
Parasitic Delay: p
0 1 2 3 4 5
0
1
2
3
4
5
6
Electrical Effort:
h = Cout / Cin
Normalized
Delay:
d
Inverter
2-input
NAND
g =
p =
d =
g =
p =
d =
0 1 2 3 4 5
0
1
2
3
4
5
6

Computing Logical Effort
• DEF: Logical effort is the ratio of the input capacitance of a gate to
the input capacitance of an inverter delivering the same output
current.
• Measure from delay vs. fanout plots
• Or estimate by counting transistor widths
A Y
A
B
Y
A
B
Y
1
2
1 1
2 2
2
2
4
4
Cin
= 3
g = 3/3
Cin
= 4
g = 4/3
Cin
= 5
g = 5/3

Catalog of Gates
• Logical effort of common gates
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8

Catalog of Gates
• Parasitic delay of common gates
• In multiples of pinv (1)
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8

Example: Ring Oscillator
• Estimate the frequency of an N-stage ring oscillator
Logical Effort: g = 1
Electrical Effort: h = 1
Parasitic Delay: p = 1
Stage Delay: d = 2
Frequency: fosc = 1/(2*N*d) = 1/4N
31 stage ring oscillator in
0.6 m process has
frequency of ~ 200 MHz

Example: FO4 Inverter
• Estimate the delay of a fanout-of-4 (FO4) inverter
Logical Effort: g = 1
Electrical Effort: h = 4
Parasitic Delay: p = 1
Stage Delay: d = 5
d
The FO4 delay is about
300 ps in 0.6 m process
15 ps in a 65 nm process

Multistage Logic Networks
• Logical effort generalizes to multistage networks
• Path Logical Effort
• Path Electrical Effort
• Path Effort
i
G g
= 
out-path
in-path
C
H
C
=
i i i
F f g h
= =
 
10
x
y z
20
g1 = 1
h1
=x/10
g2 =5/3
h2
=y/x
g3 =4/3
h3
=z/y
g4 = 1
h4
=20/z

Multistage Logic Networks
• Logical effort generalizes to multistage networks
• Path Logical Effort
• Path Electrical Effort
• Path Effort
• Can we write F = GH?
i
G g
= 
out path
in path
C
H
C
−
−
=
i i i
F f g h
= =
 

Paths that Branch
• No! Consider paths that branch:
G = 1
H = 90 / 5 = 18
GH = 18
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH
5
15
15
90
90

Branching Effort
• Introduce branching effort
• Accounts for branching between stages in path
• Now we compute the path effort
• F = GBH
on path off path
on path
C C
b
C
+
=
i
B b
=  i
h BH
=

Note:

Multistage Delays
• Path Effort Delay
• Path Parasitic Delay
• Path Delay
F i
D f
= 
i
P p
= 
i F
D d D P
= = +


Designing Fast Circuits
• Delay is smallest when each stage bears same effort
• Thus minimum delay of N stage path is
• This is a key result of logical effort
• Find fastest possible delay
• Doesn’t require calculating gate sizes
i F
D d D P
= = +

1
ˆ N
i i
f g h F
= =
1
N
D NF P
= +

Gate Sizes
• How wide should the gates be for least delay?
• Working backward, apply capacitance transformation to find input
capacitance of each gate given load it drives.
• Check work by verifying input cap spec is met.
ˆ
ˆ
out
in
i
i
C
C
i out
in
f gh g
g C
C
f
= =
 =

Example: 3-stage path
• Select gate sizes x and y for least delay from A to B
8
x
x
x
y
y
45
45
A
B

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27
Electrical Effort H = 45/8
Branching Effort B = 3 * 2 = 6
Path Effort F = GBH = 125
Best Stage Effort
Parasitic Delay P = 2 + 3 + 2 = 7
Delay D = 3*5 + 7 = 22 = 4.4 FO4
8
x
x
x
y
y
45
45
A
B
3
ˆ 5
f F
= =

• Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10
P: 4
N: 4
45
45
A
B
P: 4
N: 6
P: 12
N: 3
8
x
x
x
y
y
45
45
A
B

Best Number of Stages
• How many stages should a path use?
• Minimizing number of stages is not always fastest
• Example: drive 64-bit datapath with unit inverter
D = NF1/N + P
= N(64)1/N + N
1 1 1 1
8 4
16 8
2.8
23
64 64 64 64
Initial Driver
Datapath Load
N:
f:
D:
1
64
65
2
8
18
3
4
15
4
2.8
15.3
Fastest

Derivation
• Consider adding inverters to end of path
• How many give least delay?
• Define best stage effort
N - n1
ExtraInverters
Logic Block:
n1
Stages
Path EffortF
( )
1
1
1
1
N
n
i inv
i
D NF p N n p
=
= + + −

1 1 1
ln 0
N N N
inv
D
F F F p
N

= − + + =

( )
1 ln 0
inv
p  
+ − =
1
N
F
 =

Best Stage Effort
• has no closed-form solution
• Neglecting parasitics (pinv = 0), we find  = 2.718 (e)
• For pinv = 1, solve numerically for  = 3.59
( )
1 ln 0
inv
p  
+ − =

Sensitivity Analysis
• How sensitive is delay to using exactly the best number of stages?
• 2.4 <  < 6 gives delay within 15% of optimal
• We can be sloppy!
• I like  = 4
1.0
1.2
1.4
1.6
1.0 2.0
0.5 1.4
0.7
N / N
1.15
1.26
1.51
( =2.4)
(=6)
D(N)
/D(N)
0.0

Example, Revisited
• Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive
processor. Help Ben design the decoder for a register file.
• Decoder specifications:
• 16 word register file
• Each word is 32 bits wide
• Each bit presents load of 3 unit-sized transistors
• True and complementary address inputs A[3:0]
• Each input may drive 10 unit-sized transistors
• Ben needs to decide:
• How many stages to use?
• How large should each gate be?
• How fast can decoder operate?
A[3:0] A[3:0]
16
32 bits
16
words
4:16
Decoder
Register File

Number of Stages
• Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3) / 10 = 9.6
Branching Effort: B = 8
• If we neglect logical effort (assume G = 1)
Path Effort: F = GBH = 76.8
Number of Stages: N = log4F = 3.1
• Try a 3-stage design

Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2
Path Effort: F = GBH = 154
Stage Effort:
Path Delay:
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]
word[0]
word[15]
96 units of wordline capacitance
10 10 10 10 10 10 10 10
y z
y z
1/3
ˆ 5.36
f F
= =
ˆ
3 1 4 1 22.1
D f
= + + + =

Comparison
• Compare many alternatives with a spreadsheet
• D = N(76.8 G)1/N + P
Design N G P D
NOR4 1 3 4 234
NAND4-INV 2 2 5 29.8
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6

Review of Definitions
Term Stage Path
number of stages
logical effort
electrical effort
branching effort
effort
effort delay
parasitic delay
delay
i
G g
= 
out-path
in-path
C
C
H =
N
i
B b
= 
F GBH
=
F i
D f
= 
i
P p
= 
i F
D d D P
= = +

out
in
C
C
h =
on-path off-path
on-path
C C
C
b
+
=
f gh
=
f
p
d f p
= +
g
1

Method of Logical Effort
1) Compute path effort
2) Estimate best number of stages
3) Sketch path with N stages
4) Estimate least delay
5) Determine best stage effort
6) Find gate sizes
F GBH
=
4
log
N F
=
1
N
D NF P
= +
1
ˆ N
f F
=
ˆ
i
i
i out
in
g C
C
f
=

Limits of Logical Effort
• Chicken and egg problem
• Need path to compute G
• But don’t know number of stages without G
• Simplistic delay model
• Neglects input rise time effects
• Interconnect
• Iteration required in designs with wire
• Maximum speed only
• Not minimum area/power for constrained delay

FET POWER & DELAY/FREQUENCY TECHNIQUES

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