1. Operational Transconductance Single-Ended Amplifier
Group 1 Helion Dhrimaj and Murat Yokus
Date: 12/7/2104

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Academic Integrity Statement
Academic Integrity Pledge
Plagiarism is defined as copying the language, phrasing, structure, or specific ideas of others and
presenting any of these as one's own, original work; it includes buying papers, having someone
else write your papers, and improper citation and use of sources. When you present the words or
ideas of another (either published or unpublished) in your writing, you must fully acknowledge
your sources. Plagiarism is considered a violation of academic integrity whenever it occurs in
written work, including drafts and homework, as well as for formal and final papers.
The NCSU Policies, Regulations, and Rules on Student Discipline
(http://www.ncsu.edu/policies/student_services/student_discipline/POL11.35.1.php) sets the
standards for academic integrity at this university and in this course. Students are expected to
adhere to these standards. Plagiarism and other forms of academic dishonesty will be handled
through the university's judicial system and may result in failure for the project or for the course.
Pledge:
We have read and understood the above statement and agree to abide by the standards of academic
integrity in the NCSU Policies, Regulations, and Rules on Student Discipline.
Team members:
Helion Dhrimaj
Murat Yokus

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Table of Contents
Executive Summary........................................................................................................................ 5
OTA Design Discussion ................................................................................................................. 6
Input Stage Design...................................................................................................................... 6
Output Stage Design ................................................................................................................... 7
Gain Boosting Op-Amp (Baby Op-Amp) Design ...................................................................... 8
Supply Independent Biasing Circuit Design............................................................................... 9
Compensation ........................................................................................................................... 10
Circuit Schematics ........................................................................................................................ 14
Parameter Values ...................................................................................................................... 14
DC Operating Points................................................................................................................. 17
Results........................................................................................................................................... 20
Conclusion and Discussion........................................................................................................... 26

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Table of Figures
Figure 1. Input design of main stage on the left and right ............................................................. 6
Figure 2. Output design of main stage........................................................................................... 7
Figure 3. NMOS gain boosting op-amp design ............................................................................. 8
Figure 4. PMOS gain boosting op-amp design.............................................................................. 8
Figure 6. Constant gm-biasing design ........................................................................................... 9
Figure 7. AC gain of NMOS gain boosting before compensation............................................... 10
Figure 8. AC gain of NMOS gain boosting after compensation.................................................. 11
Figure 9. AC gain of PMOS gain boosting amplifier before compensation................................ 11
Figure 10. AC gain of PMOS gain boosting amplifier after compensation................................. 12
Figure 11. Main gain stage before compensation ........................................................................ 13
Figure 12. Main gain stage after compensation........................................................................... 13
Figure 13. NMOS gain boosting amplifier parameter values...................................................... 14
Figure 14. PMOS gain boosting operational amplifer parameter values..................................... 15
Figure 15. Biasing circuit parameter values ................................................................................ 16
Figure 16. Main gain stage parameter values .............................................................................. 16
Figure 17. DC operating points of NMOS gain boosting op-amp............................................... 17
Figure 18. DC operating points of PMOS gain boosting op-amp................................................ 18
Figure 19. DC operating point of biasing circuit......................................................................... 18
Figure 20. DC operating points of main gain stage ..................................................................... 19
Figure 21. Frequency response of the OTA................................................................................. 20
Figure 22. CMRR, differential gain, and common mode gain .................................................... 21
Figure 23. PSRR, differential gain as well as Vdd gain .............................................................. 22
Figure 24. Input common mode ranges between 0.34 and 1.65 V .............................................. 22
Figure 25. Single ended output swing range from .601-2.072 Volts........................................... 23
Figure 26. Noise voltage floor at 272.519 MHz .......................................................................... 23
Figure 27. Slew Rate and Settling Times Results........................................................................ 24
Figure 28. Slew Rate at VDC = 2.25 ........................................................................................... 24
Figure 29. GBW at VDC = 2.25 V .............................................................................................. 25

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Executive Summary
Our single ended operational OTA provides 80 dB gain with a unity gain bandwidth of 198
MHz and a 64.65 degree phase margin. Our circuit’s input common mode range is from 0.34-
1.65V and the output swing is 1.8 V peak to peak. The settling time of our circuit is well below
the 90nsec specification at 37.39nsec and the slew rate reaches 79.439 V/usec. The flicker noise
floor at 272.52 MHz has a value of 6.8181nV/√𝐻𝑧 . Finally the OTA dissipates only 1.029 mW.
Table 1. Project Specifications
Parameter Required Specification Achieved Specification
Low-Frequency Gain 80 dB 80 dB
Gain-bandwidth product >175 MHz 198 MHz
Phase Margin 75 degrees, w/ unity gain fb,
no external load
64.65 degrees
Settling time <90nsec with 4pF external
load
37.29 nsec
Output Swing 1.2 V-pk-pk single ended 1.4 V-pk-pk single ended
Input common-mode range Rail to rail operation (0-2.5V) 0.34 – 1.65
CMRR >100 dB 113.863 dB
PSRR+ >100 dB 73.4 dB
Supply Voltage 2.5V 2.5 V
Power dissipation Pdiss<12 mW 1.029 mW (409.97µsec)
Slew rate >18 V/usec 79.439 V/usec
Input referred noise voltage
floor
<10 nV/√𝐻𝑧 in white portion
Also, you must report the 1/f
frequency
6.8181 nV/√𝐻𝑧
at 272.52 MHz
Robustness You must simulate your
design over a +/- 10% supply
voltage and over the process
corners. The GBW product
and slew rate should be
maintained within 5%
Slew rate: 55.13466 V/usec at
2.25 V
GBW: 102.7981 MHz at 2.25
V

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OTA Design Discussion
Input Stage Design
Our initial plan was to implement rail to rail input common voltage to be able to obtain
wide input range, so we chose the rail to rail input design. The width and length ratios of transistors
were arbitrarily chosen to obtain similar gm in NMOS and PMOS transistor sides. Tail currents of
340µA on both the NMOS and PMOS sides were used which ultimately gave high slew rates. This
level of current allowed us to achieve the minimum of 80 dB gain.
Figure 1. Input design of main stage on the left and right

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Output Stage Design
In order to achieve the 80 dB of gain, we created a high output resistance output stage.
Since a single ended output was used, a diode connection was made from outn to Vbp2 as shown
below. Approximately ~170 uA flows through the top and bottom transistor. Furthermore the same
time the vdsats are maintained to a value lower than 0.2 V, which was designed to enable wide
input common mode range.
Figure 2. Output design of main stage

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Gain Boosting Op-Amp (Baby Op-Amp) Design
Since our output stage achieved around 58 dB of gain, our circuit required the
implementation of NMOS and PMOS gain boosting op amps. With addition of gain boosting
stages, we achieved total gain of 80 dB. The gain boosting stage utilizes a differential input, refer
to Fig. 3. The negative inputs of baby opamps are designed to have approximately Vdsat and Vdd-
Vdsat values for NMOS and PMOS transistors respectivey in output stage.
Figure 3. NMOS gain boosting op-amp design
Figure 4. PMOS gain boosting op-amp design

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Supply Independent Biasing Circuit Design
The biasing circuit was one of the most important designs. We decided to utilize the
constant gm biasing circuit that is less sensitive to changes coming from the Vdd supply.
Furthermore, upon biasing the transistors correctly, we were able to change the value of the current
developed by varying the resistor. Our circuit required the need for voltages ranging from ~0.2 to
2.3 V. We experienced difficulties with the obtaining voltages at these limits, especially the 2.3 V
bias.
Figure 5. Constant gm-biasing design

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Compensation
In order to ensure stability, we used capacitors for compensation in the main OTA stage as
well as the gain boosting amplifiers that we used in conjunction with our main stage. In the NMOS
gain boosting stage, we used a value of 250 fF for our compensation capacitor. The output results
of our baby op amps before and after compensation are presented below.
Figure 6. AC gain of NMOS gain boosting before compensation

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Figure 7. AC gain of NMOS gain boosting after compensation
The same plots are presented below for the PMOS gain boosting amplifier. In this case a
capacitor with a value of 500fF is used for compensation.
Figure 8. AC gain of PMOS gain boosting amplifier before compensation

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Figure 9. AC gain of PMOS gain boosting amplifier after compensation
In the main stage of our OTA, we used a capacitor value of 1.5pF in order to obtain the
appropriate phase margin. We did parameter sweep to determine the value of the compensation
capacitor. Higher capacitor values gave required phase margin, however, the gain bandwidth
product value decreased to approx. 100 MHz. Therefore, we kept the value of capacitor as 1.5 pF
to be able to meet the GBW requirement. With this capacitor value, we obtained the phase margin
value as around 64 degrees.

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Figure 10. Main gain stage before compensation
Figure 11. Main gain stage after compensation

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Circuit Schematics
In this section we will include parameter values and dc values of our circuit schematics.
These include the gain boosting NMOS and PMOS op-amps, the gain stage of the amplifier with
the gain boosting op-amps, as well as the biasing circuit.
Parameter Values
Figure 12. NMOS gain boosting amplifier parameter values

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Figure 13. PMOS gain boosting operational amplifer parameter values

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Figure 14. Biasing circuit parameter values
Figure 15. Main gain stage parameter values

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DC Operating Points
Figure 16. DC operating points of NMOS gain boosting op-amp

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Figure 17. DC operating points of PMOS gain boosting op-amp
Figure 18 DC operating point of biasing circuit

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Figure 19 DC operating points of main gain stage

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Results
In this section the test results performed according to provided testing tutorials.
a) Frequency response of the OTA
Figure 20. Frequency response of the OTA

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b) Common Mode Rejection Ration
Figure 21. CMRR, differential gain, and common mode gain
c) Power Supply Rejection Ratio

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Figure 22. PSRR, differential gain as well as Vdd gain
d) Input Common Mode Range
Figure 23. Input common mode ranges between 0.34 and 1.65 V
e) Output Swing Range

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Figure 24. Single ended output swing range from .601-2.072 Volts
f) Input-Referred Noise Voltage Floor
Figure 25. Noise voltage floor at 272.519 MHz
g) Slew Rate and Settling Time

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Figure 26. Slew Rate and Settling Times Results
h) Robustness
Figure 27. Slew Rate at VDC = 2.25

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Figure 28. GBW at VDC = 2.25 V

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Conclusion and Discussion
In this project we designed and built a single ended OTA with 0.25µm CMOS technology.
Our designed and simulated circuit achieved 80 dB low frequency gain, a unity gain bandwidth of
198 MHz, as well as a phase margin of 64.6 degrees. The input common-mode range is from 0.34
to 1.65 with an output swing range of 1.8V peak to peak.
Our initial goal was to build a fully differential amplifier. We first achieved the proper
gain, GBW, and phase margin with the single ended output. From here we constructed the common
mode feedback circuit that proved to lower gain significantly. The CMFB circuitry did not perform
well when upon differential voltage changes in output stage. Therefore, we did not include the
CMFB design in our project.
We also noticed that when we incorporated the biasing circuit (initially ideal current and
voltage sources were used), the current values on input stage and output stage varied slightly. To
be able to obtain close current values that we had with ideal current sources in input and output
stages, we increased the length of the diode connected and its complementary transistor to
eliminate the effect of channel length modulation.
We have not met the phase margin, PSRR, rail to rail input, and robustness specifications.
Including a Gm optimization stage that enables a constant Gm over a wide range of input voltages
(0-2.5V). Further optimization is necessary in sizes of the transistor to be able to meet the
requirements. Our circuit design had low power consumption (approx. 1mW). Since the required
power consumption value is less than 12mW, more focus can be obtained to use the power
efficiently to be able to meet most of the requirements.
References
[1] D.A. Johns and K. Martin, “Chapter 6 – Advanced Current Mirrors and OpAmps,” in Analog
Integrated Circuit Design, 1st
ed. New York, John Wiley & Sons, Inc., 1997, pp. 256-266.
[2] Analog Circuit Design Class Notes, Fall 2014.