1. An investigation into the impact of surface
passivation techniques using metal-
semiconductor interfaces
Y. Bonyadi1, P.M. Gammon1, Y.K. Sharma2, G. Baker1*, P.A. Mawby1
1 School of Engineering, University of Warwick, Coventry, CV4 7AL, UK
2 Dynex Semiconductor Ltd, Lincoln, UK
Introduction & Objectives
Schottky barrier diodes (SBDs) were formed on untreated 4H-SiC
surfaces, and after thermal oxidation, direct N2O growth, and direct PSG
growth have been performed, and the resulting oxides removed. Then
Mo, Ni, and Ti SBDs were fabricated to study the impact of the surface
passivation techniques using these metal-semiconductor interfaces.
These diodes were then characterised using Current-Voltage (I-V),
Capacitance-Voltage (C-V), and Current-Voltage-Temperature (I-V-T)
analysis.
Background
Minimising the interface traps density (Dit) is vital for realising the
advantageous properties of 4H-SiC devices. The existence of interface
traps/defects, which originate from dangling bonds and carbon clusters is a
major obstacle in development of SiC MOS devices [1]. Hence, several
passivation treatments have been investigated to improve the surface quality
and passivate traps after oxide growth [2]:
• Direct Nitrogen growth
• Direct Phosphorus growth
Table 1. Each result is the average of at least 7 of each diode tested.
Results and Discussion
Fig. 4 Forward characteristics of (a) Mo/SiC, (b) Ni/SiC and (c) Ti/SiC SBDs using different surface passivation treatments.
Fig. 2 (a) Forward and (b) Reverse I-V-T characteristics of PSG treated Mo/SiC at different
temperatures.
Fig. 3 The C-2-V used to extract the doping value
(N2O treated diodes before contact annealing).
1. After depositing a contact metal (Mo, Ni and Ti), but prior to contact annealing (no silicides were formed), IVT and C-V measurements helped
assess the effects of the passivation treatments on the SiC surface.
2. After annealing the contacts and the formation of metal silicides at the interface, the same electrical characterisation techniques were used
to examine the impact of these treatments on SBDs themselves. Fig. 1 SBD Cross section
schematic.
In Table 1, the SBH extracted from C-V analysis before contact annealing show just 0.14
eV variation across all the diodes, suggesting that the interface is greatly suffering from
Fermi-Level pinning, the result of significant interface traps. Contact annealing process
largely reduced the amount of charge at the metal-semiconductor interface. The
surface treatments result in SBH lowering and doping profile dropping. No
improvement was observed in ideality factor.
The doping extracted from C-V data varies from the Ni diodes, at the expected value of 4×1015 cm-3, to the Ti (~3×1015 cm-3) and Mo diode (~2×1015 cm-3). This occurs
due to bending in the C-2-V used to extract the value which is most pronounced in the Mo, and the result of charge at the interface that skews the measurement (Fig.3)
Experimental Details
An unexpected result from this work was the performance of
PSG treated Mo diodes. These appear to break the trade-off
between turn-on voltage and leakage current by having a low
barrier height (consistent with all the Mo and Ti diodes), but
also the lowest leakage of any device (4.44×10-5 A/cm2). Even
when tested at 300°C, a leakage of 7.26×10-4 A/cm2 is lower
than any of the other devices at room temperature (Fig.2)
Conclusions
• Although, the results of this study did not reveal any consistent patterns between the different treatments, a Mo diode formed on a surface after PSG treatment, displays
exceptionally low leakage (4.44×10-4 A/cm2 at 19°C). Even when tested at 300°C, a leakage of 7.26×10-4 A/cm2 is lower than any of the other devices at room temperature.
• Barrier heights extracted from C-V analysis before contact annealing show a variation across all the diodes, suggesting that the interface is greatly suffering from
Fermi-Level pinning, the result of significant interface traps. After contact annealing the amount of charge at the metal-semiconductor interface was largely
reduced and both I-V and C-V data showed the expected work function dependence.
*Guy.Baker@Warwick.ac.uk
![An investigation into the impact of surface
passivation techniques using metal-
semiconductor interfaces
Y. Bonyadi1, P.M. Gammon1, Y.K. Sharma2, G. Baker1*, P.A. Mawby1
1 School of Engineering, University of Warwick, Coventry, CV4 7AL, UK
2 Dynex Semiconductor Ltd, Lincoln, UK
Introduction & Objectives
Schottky barrier diodes (SBDs) were formed on untreated 4H-SiC
surfaces, and after thermal oxidation, direct N2O growth, and direct PSG
growth have been performed, and the resulting oxides removed. Then
Mo, Ni, and Ti SBDs were fabricated to study the impact of the surface
passivation techniques using these metal-semiconductor interfaces.
These diodes were then characterised using Current-Voltage (I-V),
Capacitance-Voltage (C-V), and Current-Voltage-Temperature (I-V-T)
analysis.
Background
Minimising the interface traps density (Dit) is vital for realising the
advantageous properties of 4H-SiC devices. The existence of interface
traps/defects, which originate from dangling bonds and carbon clusters is a
major obstacle in development of SiC MOS devices [1]. Hence, several
passivation treatments have been investigated to improve the surface quality
and passivate traps after oxide growth [2]:
• Direct Nitrogen growth
• Direct Phosphorus growth
Table 1. Each result is the average of at least 7 of each diode tested.
Results and Discussion
Fig. 4 Forward characteristics of (a) Mo/SiC, (b) Ni/SiC and (c) Ti/SiC SBDs using different surface passivation treatments.
Fig. 2 (a) Forward and (b) Reverse I-V-T characteristics of PSG treated Mo/SiC at different
temperatures.
Fig. 3 The C-2-V used to extract the doping value
(N2O treated diodes before contact annealing).
1. After depositing a contact metal (Mo, Ni and Ti), but prior to contact annealing (no silicides were formed), IVT and C-V measurements helped
assess the effects of the passivation treatments on the SiC surface.
2. After annealing the contacts and the formation of metal silicides at the interface, the same electrical characterisation techniques were used
to examine the impact of these treatments on SBDs themselves. Fig. 1 SBD Cross section
schematic.
In Table 1, the SBH extracted from C-V analysis before contact annealing show just 0.14
eV variation across all the diodes, suggesting that the interface is greatly suffering from
Fermi-Level pinning, the result of significant interface traps. Contact annealing process
largely reduced the amount of charge at the metal-semiconductor interface. The
surface treatments result in SBH lowering and doping profile dropping. No
improvement was observed in ideality factor.
The doping extracted from C-V data varies from the Ni diodes, at the expected value of 4×1015 cm-3, to the Ti (~3×1015 cm-3) and Mo diode (~2×1015 cm-3). This occurs
due to bending in the C-2-V used to extract the value which is most pronounced in the Mo, and the result of charge at the interface that skews the measurement (Fig.3)
Experimental Details
An unexpected result from this work was the performance of
PSG treated Mo diodes. These appear to break the trade-off
between turn-on voltage and leakage current by having a low
barrier height (consistent with all the Mo and Ti diodes), but
also the lowest leakage of any device (4.44×10-5 A/cm2). Even
when tested at 300°C, a leakage of 7.26×10-4 A/cm2 is lower
than any of the other devices at room temperature (Fig.2)
Conclusions
• Although, the results of this study did not reveal any consistent patterns between the different treatments, a Mo diode formed on a surface after PSG treatment, displays
exceptionally low leakage (4.44×10-4 A/cm2 at 19°C). Even when tested at 300°C, a leakage of 7.26×10-4 A/cm2 is lower than any of the other devices at room temperature.
• Barrier heights extracted from C-V analysis before contact annealing show a variation across all the diodes, suggesting that the interface is greatly suffering from
Fermi-Level pinning, the result of significant interface traps. After contact annealing the amount of charge at the metal-semiconductor interface was largely
reduced and both I-V and C-V data showed the expected work function dependence.
*Guy.Baker@Warwick.ac.uk](https://image.slidesharecdn.com/ca45c804-b62d-4f38-beba-3b4274daaa31-161031225817/85/poster-1-320.jpg)
