1. “Modeling System behaviors”….A better Paradigm on
prototyping
-Nilesh Ranpura

2. Electronic System Structure
System
development
process
Software input/output
Hardware input/output
Software Hardware
Abstraction trade offs
development development
process process

3. System Abstraction and Development Process
System Development happens this way Design Flow
Because,
1. “Abstraction layers” ensure Concept Architecture
specs
threads running concurrently
2. Different approach of specs SPI 5
Chip/Block specs
due to different types of team
Hardware
3. More than one customer with and
Board/proto specs proto specs
different nature/features
Product Specs
Not
documented
System data/environment
Reference Platforms

4. Which are those System Properties ?
Hardware
& Environmental
Software
co-exist
System Safety/
Mixed Signal Properties Standards/
Compliance
New
Performance Approaches :
Error injection Green mode

5. (1)PCIe Switch Applications – System Interconnect
Compute Blade Compute Blade Compute Blade
Memory
Memory CPU CPU Memory
Memory Memory
Memory CPU CPU Memory
Memory Memory
Memory CPU CPU Memory
Memory
I/O Hub I/O Hub I/O Hub
PCIe PCIe
Inter-Domain Switch Inter-Domain Switch
PCIe
System Interconnect
Switch
Storage Local I/O Blade
Blade Storage
Processor
Processor
Processor
Fibre Channel
SATA / SAS Expander Dual GbE Dual GbE
Controller
Controller Controller
FC FC GbE GbE GbE GbE

6. Model parameter Values
Parameter Value Remark
MPS 128 Testbench
Payload 128/256/512 Testcase
Packet types MRD,MWR,IRD Testcase
Traffic pattern Multicast, One to one, Testbench
Many to one
Speed 2.5Ghz, 5Ghz Testcase
State PM or non PM Testbench
Active Port 2/4/5/6/8 Testcase
No of packets 20/100/500/5000 Testcase
Misc. ECRC, etc

7. Model Latency definition
 Latency is the delay between starting and completing action
 Latency Definition:
Payload Switch efficiency
Theoretical(GBps) Actual throughput (GBps)
(Bytes) (Actual/Theoretical) %
32 2.462 2.000 81%
64 3.048 2.905 95%
128 3.459 3.360 97%
 Throughput (pkts/sec) = (total number of pkts(i.e. 500)/(time_t1 - time_t0))
 Throughput (bits/sec) = (throughput (pkts/sec) * length * 32)
In this case, length = Payload size + 3DW header
Theoretical max throughput assumes a 20 byte framing overhead on top of payload.
 After removing 8b/10 coding, useful x8 Gen2 unidirectional throughput is 4 GB/s.
 (4 GBps * payload) / (payload + 20) = theoretical max (second column above)

8. Usage Model and Error Model
CPU CPU
P2P NTB NTB NTB NTB P2P
CPU Memory
CPU Memory
P2P P2P P2P P2P P2P P2P P2P P2P
I/O
I/O I/O I/O I/O I/O I/O I/O I/O Hub I/O
Hub
...
.
.
.
. ...
PCIe
Switch PCIe
Switch
I/O I/O
1GbE 1GbE I/O I/O
1GbE 1GbE
Internal Switch Error
External Error

9. (2)Modeling Channel properties and Mixed
signal for Simple Link
1. Model as much as digital blocks up to last stage
2. Last analog Transceiver can be modelled and
converted
in to Differential digital by just inverting it.
3. Next slide depicts digital noise and
transmission model

10. (2)Introduce Digital Noise
•Inversion
•bit stuffing
•dummy bits
Noise Model
22
20 •Inversion
15 8 bit value of
5 •bit stuffing
20(sample value) •dummy bits
4
3
Noise Model
1. Send 22, 20. 15, 5(which are analog sample’s value) in digital
format but in parallal. So no. of data lines = no. of analog
samples * 8 bit
2. Introduce noise in numbers by inversion or value changing.

11. (2)Actual System
High speed PHY MAC
PAM modulation and Signal path
processing block

12. (2)Actual System
High speed PHY MAC
•Inversion
•bit stuffing
•dummy bits
Noise Model
PAM modulation and Signal path
processing block
1. Modeled PAM modulation scheme over digital block
2. Created noise model to make noise variation between -20dB
to 30dB for high speed signals on Cable.
3. Simulated virtual NEXT, FEXT, ISI with predictable noise
model.
4. Loop back and system loop back mode tested

13. Thank You, All…!