Personal Information
Unternehmen/Arbeitsplatz
Toulouse Area, France France
Beruf
Principal Engineer at NXP Semiconductors
Branche
Electronics / Computer Hardware
Webseite
amssocverification.blogspot.fr/
Info
20 years experience in semiconductors (digital and analog)
Mixed-signal IC verification
- Advanced Mixed-Signal Verification techniques: Hybrid module-based/UVM testbench (drivers, monitors, sequencer, digital and analog parameter randomization), Metric Driven Verification, Functional coverage (mixed-signal assertions), automatic verification plan (vPlan) update (regressions), accurate Verilog-AMS and fast Wreal modeling, SystemVerilog, DPI, VPI.
- Motion Sensors verification
- Complex Power-Management, Audio and User interface IC (1+ million components)
International Team Lead & Project Management
- Multi-cultural context (US, Europe, India)
- Organize tasks and plannings, priorities,...
Tags
verification
mixed-signal
systemverilog
monitoring
continuous-time
coverage
emanager
verilog ams
asic
bind
systemverilog; assertions
assertions
analog
verilog-ams
semantics
mixed signal
testbench
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Präsentationen
(3)Dokumente
(7)Personal Information
Unternehmen/Arbeitsplatz
Toulouse Area, France France
Beruf
Principal Engineer at NXP Semiconductors
Branche
Electronics / Computer Hardware
Webseite
amssocverification.blogspot.fr/
Info
20 years experience in semiconductors (digital and analog)
Mixed-signal IC verification
- Advanced Mixed-Signal Verification techniques: Hybrid module-based/UVM testbench (drivers, monitors, sequencer, digital and analog parameter randomization), Metric Driven Verification, Functional coverage (mixed-signal assertions), automatic verification plan (vPlan) update (regressions), accurate Verilog-AMS and fast Wreal modeling, SystemVerilog, DPI, VPI.
- Motion Sensors verification
- Complex Power-Management, Audio and User interface IC (1+ million components)
International Team Lead & Project Management
- Multi-cultural context (US, Europe, India)
- Organize tasks and plannings, priorities,...
Tags
verification
mixed-signal
systemverilog
monitoring
continuous-time
coverage
emanager
verilog ams
asic
bind
systemverilog; assertions
assertions
analog
verilog-ams
semantics
mixed signal
testbench
Mehr anzeigen