1. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 1
Accelerated System DV
Through Reuse
Edward Arthur/John Cashman/Tim Ganley/Mark Strickland
Cisco Systems, Inc.

2. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 2
Agenda
Why Perform Multi-ASIC Simulation?
The Challenges of Multi-ASIC Simulation
The Socketsim Tool
The Testbench Methodology
Other System Simulation Considerations
Summary

3. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 3
The Reality
Cisco is a large geographically diverse company
Large 10M+ gate ASICs are developed by different teams
Each team could (and probably will) have its own tool flow and
methodology
System simulation typically occurs late in development cycle
The chips need need to interoperate!

4. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 4
System Level Bugs – Connection Error
Each ASIC works on its own, but is not connected
consistently with the ASIC specs at the higher level
ASIC
X
ASIC
Y
Out[1]
Out[0]
In[0]
In[1]
Problem

5. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 5
System-Level Bugs – Specification Mismatch
Each component matches its spec, but system does not
work
translate input
value A to
output value B
System Spec
ASIC
X
ASIC
Y
System Block Diagram
translate A to 5 translate 6 to B
ASIC X Spec ASIC Y Spec
RTL TB= RTL TB=
Sim OK Sim OK
Problem

6. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 6
ASIC DV Escape – Broad Input Behavior
Not all combinations of possible input space were tried
in ASIC DV; specific behavior from source ASIC causes
a problem
ASIC X Spec
A
5 clocks
B
12 clocks
C
This combination not
tested in DV for Y and
reveals a bug
ASIC
X
ASIC
Y
ASIC Y Spec
A
1 to 200 clocks
B
1 to 200 clocks
C
A
B
C
40,000 timing
combinations

7. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 7
Commonly Discovered System Issues
FIFO Depth Assumptions – e.g. SPI4.2 LMax on/off
Physical layer interface interoperability – e.g. Flow
Control
Internal header transport and signaling protocol
interoperability – e.g. Priority bit interpretation
Reset Sequence
Performance
Validation of end-to-end flow control

8. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 8
Agenda
Why Perform Multi-ASIC Simulation?
The Challenges of Multi-ASIC Simulation
The Socketsim Tool
The Testbench Methodology
Other System Simulation Considerations
Summary

9. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 9
System Simulation Challenges
Technical issues
– System resources (memory)
– Different high-level verification languages (HVLs)
– Encrypted IP tied to specific simulators
– Porting a design to a different simulator
– Different versions of the same HVLs or simulators
– Operating System dependencies
– Work around language issues

10. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 10
The Problem
How do we rapidly get to multi-ASIC simulation?

11. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 11
Generic Testbench Structure
Drivers
Monitors
Scoreboard
DUT
Testbench
Environment (ENV)
Running on a
single system
(SYS)
Scoreboard
ENV
DUT
driver
monitor
BFM
SYS
driver
monitor
BFM

12. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 12
2-Chip Environment
• Traditional 2-Chip Environment would take too much
effort (i.e. combining testbenches, re-architecting ENVs)
Scoreboard
ENV
DUT
SYS
driver
monitor
BFM
driver
monitor
BFM
Scoreboard
ENV
DUT1
SYS
DUT2
driver
monitor
BFM
driver
monitor
BFM
driver
monitor
BFM
Scoreboard
ENV
DUT
SYS
driver
monitor
BFM
driver
monitor
BFM

13. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 13
Ideal 2-Chip Environment
SOCKET
Goal reuse as much a possible
A socket accomplishes this goal!
• Maintain ENV and SYS of both simulations
Scoreboard
ENV1
DUT1
driver
monitor
BFM
SYS1
driver
monitor
BFM
Scoreboard
ENV2
DUT2
driver
monitor
BFM
SYS2
driver
monitor
BFM

14. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 14
Solution
Socketsim Tool – Chip-to-chip interfaces
communicate over sockets
Testbench Methodology – Chip-level
testbenches written for reuse at system-
level

15. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 15
Agenda
Why Perform Multi-ASIC Simulation?
The Challenges of Multi-ASIC Simulation
The Socketsim Tool
The Testbench Methodology
Other System Simulation Considerations
Summary

16. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 16
What is the Socketsim tool?
PLI application which monitors Verilog signals and
propagates signal changes across sockets between
environments
Provides virtual wires between two testbenches running on
different systems
Each environment syncs up each “heartbeat”
Verilog
VPI – PLI
MPICH
MPICH
VPI – PLI
Verilog
socket

17. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 17
Socketsim tool
Similar to Avery Design SimCluster tool
http://www.avery-design.com
~2,800 lines of C/C++ code
MPI underneath (MPICH 1.2.5.2)
VCS (V7.2R18+) and NC (5.3+) supported
Linux and Solaris supported
No additional license required ☺
Verilog
VPI – PLI
MPICH
MPICH
VPI – PLI
Verilog
socket

18. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 18
Socketsim PLI
Sender
Register callback on
changes of inputs to socket
Save all changes up to delta
cycle
Receiver
Replay changes on outputs
of socket applying at each
time slice
Implied wire delay over
socket equal to delta cycle
SENDER:
@heartbeat
send buffer
to remote host
RECEIVER:
Blocks waiting
for buffer,
playback
changes
SENDER:
@signal change
save value/time
to buffer

19. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 19
Socketsim Verilog instances – SPI4.2
// “Left ASIC” side
socketsim #(.IN_WIDTH(20),
.OUT_WIDTH(20))
socket(.ins({tb_spi_tx_data[15:0],
tb_spi_tx_ctl,
tb_spi_rx_stat[1:0],
tx_sync}),
.outs({tb_spi_rx_data[15:0],
tb_spi_rx_ctl,
tb_spi_tx_stat[1:0],
rx_sync}));
// “Right ASIC” side
socketsim #(.OUT_WIDTH(20),
.IN_WIDTH(20))
socket(.outs({NpRxData[15:0],
NpRxControl,
NpTstat[1:0],
rx_sync}),
.ins({NpTxData[15:0],
NpTxControl,
NpRstat[1:0],
tx_sync}));

20. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 20
More Socketsim Features
Bidirectionals supported
Heartbeat user configurable at runtime
Multiple point-to-point connections allowed
ChipA has interfaces to ChipB and ChipC
Compression supported for wiiiiiiiiiiiiiide buses
Peers communicate directly
HVL↔HVL communication
Use Verilog tasks as wrappers for signals which cross the socket

21. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 21
Agenda
Why Perform Multi-ASIC Simulation?
The Challenges of Multi-ASIC Simulation
The Socketsim Tool
The Testbench Methodology
Other System Simulation Considerations
Summary

22. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 22
Testbench Methodology
Borrowed from Cadence eRM methodology
Decouple BFM’s driver from scoreboard
BFM’s drivers should not put objects onto scoreboard
Monitors watch wires in both directions and forward information
to scoreboard
SOCKETScoreboard
ENV
DUT
driver
monitor
BFM
SYS
driver
monitor
BFM
Scoreboard
ENV
DUT
driver
monitor
BFM
SYS
driver
monitor
BFM
Put these local drivers in PASSIVE mode

23. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 23
Mechanism for synchronizing test flow
Testflow synchronization – sync up
the various phases of each
environment with sideband signal
Phases will have different
durations
Reset()
Init()
Main()
Post()
End()
ENV1
Reset()
Init()
Main()
Post()
End()
ENV2
End Simulation
Start Simulation
Socket

24. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 24
Other Sideband Signaling
Messaging Semaphore – besides the data/control signals that pass
across the socket, pass sideband signals during test for
configuration, special event or sequence (i.e. backpressure event,
register sequence)
Backpressure
event
cfg
information
SOCKET
Scoreboard
ENV
DUT
driver
monitor
BFM
SYS
driver
monitor
BFM
Scoreboard
ENV
DUT
driver
monitor
BFM
SYS
driver
monitor
BFM
Sequence
driver
Sequence
driver

25. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 25
Passing Configuration via File
File I/O - for on-the-fly configuration synchronization
Both ENVs could read common file
One ENV could write cfg, the other read it
Write_ascii_struct() Read_ascii_struct()
Scoreboard
ENV
DUT
driver
monitor
BFM
SYS
driver
monitor
BFM
Scoreboard
ENV
DUT
driver
monitor
BFM
SYS
driver
monitor
BFM
Sequence
driver
Sequence
driver
SOCKET

26. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 26
Testbench Methodology Summary
Recommended testbench methodology for multi-ASIC
system simulation:
Each BFM’s driver should not put objects onto scoreboard
Each BFM’s driver can be turned off (passive mode)
Monitors will simply place data objects on the scoreboard
Scoreboard uses data objects from monitors, system state and
transfer function to generate expected results

27. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 27
Agenda
Why Perform Multi-ASIC Simulation?
The Challenges of Multi-ASIC Simulation
The Socketsim Tool
The Testbench Methodology
Other System Simulation Considerations
Summary

28. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 28
Performance
All ENVs slow down to slowest ENV + overhead
10%-40% slowdown seen
– Each environment must sync up every heartbeat which pegs
performance to the slowest environment
– Additional overhead comes from message passing over
network

29. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 29
Performance Analysis
Parameters which will affect performance
Multiprocessor server
Cache thrashing
Memory contention
CPUs of same speed
Heartbeat duration
Varying amount work/heartbeat
How many sockets
Socket width
Startup time (compile/load/init/…)
More work needs to be done – we’ve only skimmed the surface

30. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 30
Agenda
Why Perform Multi-ASIC Simulation?
The Challenges of Multi-ASIC Simulation
The Socketsim Tool
The Testbench Methodology
Other System Simulation Considerations
Summary

31. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 31
Summary
The recommended testbench methodology (Cadence
eRM) enables efficient chip-level testbench reuse at the
system-level
Socketsim solves the problem of connecting chip-level
environments to form system-level environments
- certain environments can only be simulated this way

32. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 32
Related Documentation
http://www.avery-design.com (SimCluster tool)
http://web.archive.org/web/20060429011636/http://www.avery-
design.com/web/avery_hdlcon02.pdf (Paper describing socket simulation
techniques)

33. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 33