1. Topographical Synthesis
Shankardas Deepti Bharat
CGB0911002
VSD 532
M.Sc. [Engg.] in VLSI System Design
Module Title: Full Chip Functional Verification
Module Leader: Mr. Padmanaban K.
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2. Contents
• Introduction
• ASIC design flow
• Topographical synthesis
• Design compiler graphical
• Key benefits of Topographical synthesis
• Congestion
• Advanced Arithmetic Optimization
• Register retiming
• Conclusion
• References
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3. Introduction
• Traditionally congestion is analyzed and fixed only during the last stage of
design i.e. during P&R.
• Today this method is inefficient, as designer may be required to iterate back
to the RTL and recode the RTL source to remove congestion-causing design
characteristics.
• This iterative process between synthesis & layout is time consuming.
• These options are not optimal and can lead to missed schedules, missed
design goals and result in added costs.
Figure 1. ASIC flow
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4. ASIC design flow
Specifications
HDL
Functional
verification
Synthesis
STA Topographical
synthesis
DFT
Timing Back end
verification
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5. Topographical synthesis
• Synopsys incorporated topographical synthesis technology into DC in 2005
• Used to accurately predicts timing, area and power.
• Ensures synthesis output correlates to actual layout.
• Reduces the number of iterations required to close design goals eliminating
the need for wire load models.
• Early prediction of routing congestion and visualization of congestion hot
spots and timing issues.
• Allows RTL designers to fix design issues early, cutting time and improving
scaling predictability.
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6. Design Compiler Graphical
• DC graphical provides the designer to preview layouts to decide on whether
congestion is due to RTL structures or due to bad floor planning.
• Includes Synopsys’ virtual global-routing technology that enables designers to
predict wire-routing congestion during RTL synthesis.
• Predicts congestion "hot spots" early in the design flow.
• Provides visualization and analysis of the congested circuit regions.
• Performs synthesis optimizations to minimize congestion in these areas.
• Provides significant improvement in design time.
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7. Key benefits of Topographical Technology (1/2)
• Delivers best Quality of Results (QoR) in terms of area, timing, power and
test Correlated to physical implementation.
• Removes timing bottlenecks by creating fast critical paths.
• Offers more flexibility for users to control optimization on specific areas of
designs.
• Distributed synthesis with automated chip synthesis.
• Enables higher efficiency with integrated static timing analysis, test synthesis
and power synthesis.
• Support for multi voltage and multi supply.
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8. Key benefits of Topographical Technology (2/2)
• Designers fix real design issues while still in synthesis and generate a better start
point for physical design, eliminating costly iterations.
• Designed for RTL designers and requires no physical design expertise or changes to
the synthesis use model.
• Delivers accurate correlation to post-layout timing, area and power without the
need for WLM.
Figure 2. DC Ultra synthesis [1]
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9. Congestion
• Routing congestion occurs when the resources (tracks) needed to route a design
exceed the available resources.
• Generates a routing-friendly net list topology that minimizes highly-congested
structures and wire crossings in congested areas.
Congestion prediction
Figure 3. DC graphical results [2]
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10. Advanced Arithmetic Optimization
• To minimize performance and area impact of carry propagation, arithmetic
trees in the HDL are optimized using carry-save arithmetic techniques.
Figure 4. Arithmetic optimization [2]
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11. Powerful Critical Path Synthesis
• Performs aggressive timing driven re-structuring, mapping and gate-level
optimization.
• Logic duplication for reducing the load seen by the critical path.
• Buffer high fan out nets to improve total negative slack.
Figure 5. Register duplication [1]
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12. Register Retiming
• Performs optimization of sequential logic by moving registers through logic
boundaries to optimize timing with minimum area impact.
• Inserts pipelines registers in pure combinational circuits in order to meet
performance and area requirements.
• Used along with datapath optimization algorithms.
• All these are performed in order to improve QoR.
Figure 6. Retiming designs with registers [1] Figure 7. Retiming on combinational logic [1]
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13. Other Advantages
• Better Control of Synthesis Cost-Function Priorities and Optimization Step
It has a default cost function that prioritizes design rule requirements over timing and
area constraints.
• Infrastructure for Multicore
Using an optimized scheme of distributed &
multithreaded parallelization, which
# of days
delivers 2X improvement in runtime on
quad-core platforms.
• Supports all popular industry
standards formats
Circuit Netlist: Verilog, SystemVerilog & VHDL. Gate count
Figure 8. Single core vs. Multi core runtimes [2]
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14. Summary
• Includes comprehensive optimization algorithms to deliver best-in-class
quality of results.
• The Topographical technology ensures results that correlate to layout,
eliminating costly iterations between synthesis and physical implementation.
• It remains to be the synthesis tool of choice with its advanced feature set and
a proven track record of countless design successes.
• It provides the ability to accurately predict, visualize and alleviate routing
congestion, substantially reducing iterations between synthesis and physical
implementation.
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15. References
[1] Synopsys Inc. , (2006) ‘Design Compiler Ultra’ [online] available from
<http://www.synopsys.com/Tools/Implementation/RTLSynthesis/DCUltra/D
ocuments/DCUltra-ds.pdf>Retrieved on 26th Feb 2012
[2] Synopsys Inc. ,(2011) ‘Design Compiler Graphical’ [online] available from <
http://www.synopsys.com/tools/implementation/rtlsynthesis/dcgraphical/Pag
es/default.aspx>Retrieved on 26th Feb 2012
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16. Thank You
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17. Remarks
Sl. No. Topic Max. marks Marks
obtained
1 Quality of slides 5
2 Clarity of subject 5
3 Presentation 5
4 Effort and question handling 5
Total 20
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