Multi-Protocol Label Switching: Basics and Applications
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Multi-Protocol Label Switching has become by far one of the most important Internet technologies of the last 15 years. From humble beginnings back in 1996-97, it is literally the defacto standard in a large majority of service provider networks today. This presentation, delivered to executives at MTNL, Mumbai (a large regional carrier in India), explains the key operational principles behind MPLS, and its significant applications.
![Multi-Protocol Label Switching: Basics & Applications Dr. Vishal Sharma Email: [email_address] Web: http://www.metanoia-inc.com Metanoia, Inc. Critical Systems Thinking™ © Copyright 2002-2005 All Rights Reserved](https://image.slidesharecdn.com/mtnlmplstutorialdrvishalsharma20050426-13099618377946-phpapp01-110706092342-phpapp01/85/Multi-Protocol-Label-Switching-Basics-and-Applications-1-320.jpg)
![The Start: Routing Process at a Router ,[object Object],[object Object],[object Object]](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
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Multi-Protocol Label Switching: Basics and Applications
- 1. Multi-Protocol Label Switching: Basics & Applications Dr. Vishal Sharma Email: [email_address] Web: http://www.metanoia-inc.com Metanoia, Inc. Critical Systems Thinking™ © Copyright 2002-2005 All Rights Reserved
- 14. MPLS Header over POS or IEEE 802.3
- 15. MPLS Header over ATM
- 16. Label Assignment and Distribution (Control Component) Direction from which labels flow Refers to whether LSR distributes labels on demand or voluntarily Whether LSR waits to hear from its upstream/downstream nbrs. before responding to a request for label(s) Label Retention : Liberal or Conservative Whether LSR keeps labels from a neighbor who is not currently the next hop for a FEC Labels Data Labels Data
- 17. Example Label Assignment and Distribution Modes Edge LSR Downstream-on-demand with Independent Control Edge LSR Edge LSR Downstream-on-demand with Ordered Control 4 3 3’ Edge LSR 1 Requests 2 2’ Assignments 2 3 5 6 1 Requests 4 Assignments
- 18. Comparison of ATM Switch, IP Router, LSR, and Optical X-connect
- 23. Loose ER-LSP Setup using CR-LDP Edge LSR Edge LSR Network operator or network management creates ER-LSP request with path and traffic parameters 4.4.5.6 4.4.5.7 3.3.3.2 AS100 Label Req. <as100, 3.3.3.2> Label Req. <as100, 3.3.3.2> Label Req. <3.3.3.2> Label Mapping. Label Mapping. Label Mapping.
- 28. Utility of Hierarchical Label Switching Interior LSRs Border LSRs Swap and Push Pop Swap
- 32. TE Topology versus Regular Routed Topology
Hinweis der Redaktion
- Issues in MPLS-based Control of SDH/SONET Networks This assumes a downstream on demand with ordered control mode of label distribution. Other label distribution modes are also possible. For example, unsolicited label distribution mode.
- Good afternoon! And welcome to the course on next-generation high-performance switch architectures. Thank you for coming. Over these two days my goal is to explore some details of this subject that will lead to a deeper understanding of the operation of canonical high-speed switch architectures. Before we begin, I’d like to give you a quick overview of the course, and of the sequence in which we’ll cover the material. The material is organized into 6 parts, half of which we’ll cover today. Today, we’ll begin with an overview of some basic switching notions and look at the essential architectural components of switches and cross-connects. We’ll also look at the generic data path processing that occurs within each. We will then look at a taxonomy of switch architectures and switching fabrics. Here we’ll cover the evolution of switch/routers over several generations, and examine the properties and features of different types of switching fabrics. We’ll also review the properties of input and output queueing. Having developed an overall understanding of the architectures of switches and routers, we’ll delve next into tracing the data path through an IP router, a TDM cross-connect, and a hybrid TDM/IP switch, and look at two examples in detail – the Cisco Catalyst switch and the Juniper M Series routers. Starting tomorrow, we will start dissecting each of the three main processing steps in a switch/router--- input processing, scheduling across the switch fabric, and output queueing. We’ll look at methods, algorithms, and techniques for each with a focus on hardware complexity and implementation issues. I have factored in time for discussions, so I hope you’ll ask questions freely at any time during these lectures. This will enable me to adjust my presentations to best help you. It will also make these lectures more interesting for me. If you have additional questions, please feel free to contact me after May 6 th . My contact information is on the title slide.
- Good afternoon! And welcome to the course on next-generation high-performance switch architectures. Thank you for coming. Over these two days my goal is to explore some details of this subject that will lead to a deeper understanding of the operation of canonical high-speed switch architectures. Before we begin, I’d like to give you a quick overview of the course, and of the sequence in which we’ll cover the material. The material is organized into 6 parts, half of which we’ll cover today. Today, we’ll begin with an overview of some basic switching notions and look at the essential architectural components of switches and cross-connects. We’ll also look at the generic data path processing that occurs within each. We will then look at a taxonomy of switch architectures and switching fabrics. Here we’ll cover the evolution of switch/routers over several generations, and examine the properties and features of different types of switching fabrics. We’ll also review the properties of input and output queueing. Having developed an overall understanding of the architectures of switches and routers, we’ll delve next into tracing the data path through an IP router, a TDM cross-connect, and a hybrid TDM/IP switch, and look at two examples in detail – the Cisco Catalyst switch and the Juniper M Series routers. Starting tomorrow, we will start dissecting each of the three main processing steps in a switch/router--- input processing, scheduling across the switch fabric, and output queueing. We’ll look at methods, algorithms, and techniques for each with a focus on hardware complexity and implementation issues. I have factored in time for discussions, so I hope you’ll ask questions freely at any time during these lectures. This will enable me to adjust my presentations to best help you. It will also make these lectures more interesting for me. If you have additional questions, please feel free to contact me after May 6 th . My contact information is on the title slide.
- Good afternoon! And welcome to the course on next-generation high-performance switch architectures. Thank you for coming. Over these two days my goal is to explore some details of this subject that will lead to a deeper understanding of the operation of canonical high-speed switch architectures. Before we begin, I’d like to give you a quick overview of the course, and of the sequence in which we’ll cover the material. The material is organized into 6 parts, half of which we’ll cover today. Today, we’ll begin with an overview of some basic switching notions and look at the essential architectural components of switches and cross-connects. We’ll also look at the generic data path processing that occurs within each. We will then look at a taxonomy of switch architectures and switching fabrics. Here we’ll cover the evolution of switch/routers over several generations, and examine the properties and features of different types of switching fabrics. We’ll also review the properties of input and output queueing. Having developed an overall understanding of the architectures of switches and routers, we’ll delve next into tracing the data path through an IP router, a TDM cross-connect, and a hybrid TDM/IP switch, and look at two examples in detail – the Cisco Catalyst switch and the Juniper M Series routers. Starting tomorrow, we will start dissecting each of the three main processing steps in a switch/router--- input processing, scheduling across the switch fabric, and output queueing. We’ll look at methods, algorithms, and techniques for each with a focus on hardware complexity and implementation issues. I have factored in time for discussions, so I hope you’ll ask questions freely at any time during these lectures. This will enable me to adjust my presentations to best help you. It will also make these lectures more interesting for me. If you have additional questions, please feel free to contact me after May 6 th . My contact information is on the title slide.
- Good afternoon! And welcome to the course on next-generation high-performance switch architectures. Thank you for coming. Over these two days my goal is to explore some details of this subject that will lead to a deeper understanding of the operation of canonical high-speed switch architectures. Before we begin, I’d like to give you a quick overview of the course, and of the sequence in which we’ll cover the material. The material is organized into 6 parts, half of which we’ll cover today. Today, we’ll begin with an overview of some basic switching notions and look at the essential architectural components of switches and cross-connects. We’ll also look at the generic data path processing that occurs within each. We will then look at a taxonomy of switch architectures and switching fabrics. Here we’ll cover the evolution of switch/routers over several generations, and examine the properties and features of different types of switching fabrics. We’ll also review the properties of input and output queueing. Having developed an overall understanding of the architectures of switches and routers, we’ll delve next into tracing the data path through an IP router, a TDM cross-connect, and a hybrid TDM/IP switch, and look at two examples in detail – the Cisco Catalyst switch and the Juniper M Series routers. Starting tomorrow, we will start dissecting each of the three main processing steps in a switch/router--- input processing, scheduling across the switch fabric, and output queueing. We’ll look at methods, algorithms, and techniques for each with a focus on hardware complexity and implementation issues. I have factored in time for discussions, so I hope you’ll ask questions freely at any time during these lectures. This will enable me to adjust my presentations to best help you. It will also make these lectures more interesting for me. If you have additional questions, please feel free to contact me after May 6 th . My contact information is on the title slide.
- Issues in MPLS-based Control of SDH/SONET Networks