Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)

Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer,
AND, OR gates, buffers) on silicon chip.

www.vlsisystemdesign.com

Floorplanning is basically the arrangement of logical blocks (i.e.
multiplexer, AND, OR gates, buffers) on silicon chip.

It is attained by following steps:

• Partition and synthesize larger designs into smaller modules
consisting of IP’s and std cells




• Define width and Height of ‘core’ and ‘Die’ using the physical area of
synthesized netlist, utilization factor and aspect ratio




• Define locations of pre-placed cells




• Place de-coupling capacitors surrounding pre-placed cells




• Power Planning




• IO Pin/Pad placement


Partition and Synthesize larger designs into smaller modules
consisting of IP’s and std cells

Can Be any connection or combination
Combinational
logic Of logical cells


Combinational

For Eg.


Combinational

For Eg.

A6
A1
A4
Combinational A2 A5 A7
logic
A3


Combinational

For Eg.

A1
A5
A2
Combinational A7 A8
logic
A3
A6
A4


A6
A1
A4
logic
A3


A6
A1
A4
logic
A3

cut1

A6
A1
A4
A2 A5 A7

A3 cut2


A6
A1
A4
logic
A3

cut1 Block 1 Block 2

A6 A1 A4 A5 A6
A1
A4
A2 A5 A7 A2 A3 A7

A3 cut2


A6
A1
A4
logic
A3

cut1 Block 1 Block 2

A6 A1 A4 A5 A6
A1
A4
A2 A5 A7 A2 A3 A7

A3 cut2

Therefore, Block1 and Block2 can be called as IP’s, which are implemented separately,
and can be used multiple times in design.


This is explained as below
Block 1 Block 2

A1 A4 A5 A6

A2 A3 A7


Block 1 Block 2

A1 A4 A5 A6

A2 A3 A7

Extend IO pins

A1 A4 A5 A6

A2 A3 A7


Block 1 Block 2

A1 A4 A5 A6

A2 A3 A7

Extend IO pins

A1 A4 A5 A6

A2 A3 A7

Black Box the boxes

A1 A4 A5 A6

A2 A3 A7


Block 1 Block 2

A1 A4 A5 A6

A2 A3 A7

Black Box the boxes

A1 A4 A5 A6

A2 A3 A7


Block 1 Block 2

A1 A4 A5 A6

A2 A3 A7

Black Box the boxes

A1 A4 A5 A6

A2 A3 A7

Separate the Black Boxes as two different IP’s or modules

A1 A4

A2


Block 1 Block 2

A1 A4 A5 A6

A2 A3 A7

Black Box the boxes

A1 A4 A5 A6

A2 A3 A7


A1 A4

A2

Assign names to Pins and IP’s

Block 1 Block 2

A1 A4 A5 A6

A2 A3 A7

Black Box the boxes

A1 A4 A5 A6

A2 A3 A7


a A1 A4 o1
b
o a
c A2 o2
d


Block 1 Block 2

A1 A4 A5 A6

A2 A3 A7

Black Box the boxes

A1 A4 A5 A6

A2 A3 A7


a A1 A4 o1
b
Block 1 o a Block 2
c A2 o2
d


Let’s Try Another example


A1
A5
A2
Combinational A7 A8
logic
A3
A6
A4


A1
A5
A2
Combinational A7 A8
logic
A3
A6
A4

cut1 cut2
A1
A5
A2
A7 A8
A3
A6
A4


A1
A5
A2
Combinational A7 A8
logic
A3
A6
A4

cut1 cut2
Block 1 Block 2
A1
A5
A2 A1 A2 A5 A6
A7 A8
A3
A6 A3 A4 A7 A8
A4


A1
A5
A2
Combinational A7 A8
logic
A3
A6
A4

cut1 cut2
Block 1 Block 2
A1
A5
A2 A1 A2 A5 A6
A7 A8
A3
A6 A3 A4 A7 A8
A4

Therefore, Block1 and Block2 can be called as IP’s, which are implemented separately,
and can be used multiple times in design.

Block 1 Block 2

A1 A2 A5 A6

A3 A4 A7 A8


Block 1 Block 2

A1 A2 A5 A6

A3 A4 A7 A8

Extend IO pins

A1 A2 A5 A6

A3 A4 A7 A8


Block 1 Block 2

A1 A2 A5 A6

A3 A4 A7 A8

Extend IO pins

A1 A2 A5 A6

A3 A4 A7 A8

Black Box the boxes

A1 A2 A5 A6

A3 A4 A7 A8


Block 1 Block 2

A1 A2 A5 A6

A3 A4 A7 A8

Black Box the boxes

A1 A2 A5 A6

A3 A4 A7 A8


Block 1 Block 2

A1 A2 A5 A6

A3 A4 A7 A8

Black Box the boxes

A1 A2 A5 A6

A3 A4 A7 A8


o1 a
a A1 A2 A6
b Block 1 o2 b A5
Block 2
c o3 c
A3 A4 A7 A8 o
d o4 d


• Other combinational logic blocks which have directly offered as IP are
Mux, Clock-gating cells, ALU, etc.
• These above logical blocks are called as Re-usable blocks, i.e. they are
implemented only once, and instantiated in designs where-ever needed as
a module or IP.


• ALU is available as a re-usable block (commonly called as IP), which means,
this part of the design, need not be re-implemented, but can be instantiated
multiple times in design.

• Similarly, there are other IP’s also available, for eg.

Clock – Mux
Memory Comparator
gating
cell

• The arrangement of these IP’s in a chip is referred as Floorplanning
• These IP’s/blocks have user-defined locations, and hence are placed in chip
before automated placement-and-routing and are called as pre-placed cells.
• Automated placement and routing tools places the remaining logical cells in the
design onto chip


Block a Block b

Block c


Block a Block b

Block c

Block a Block b

Block c

Block a Block b

• The arrangement shown on top occupies Block c
minimum area, whereas the one on the
bottom occupies larger area on chip, and
hence facilitates the user to add more
Block a Block b
blocks (i.e. additional functionality) in to
the chip.

Block c

Block a Block b

• The arrangement shown on top occupies Block c
minimum area, whereas the one on the
bottom occupies larger area on chip, and
hence facilitates the user to add more
Block a Block b
blocks (i.e. additional functionality) in to
the chip.

• If, the specifications demands for minimum
area, the top arrangement is selected,

Block c
whereas, if the specification demands
decent area as well as additional
functionality, the bottom arrangement is
selected.


• The abstract level behavioral
description of the processor is
written using an RTL program.

• Large designs (e.g.
microprocessor in our case)
are usually synthesized into
small modules.

• These modules are the basic
building blocks of a
microprocessor e.g. memory
unit, adder/subtractor (ALU)
unit, multiplexer unit, etc.


• This is how the floorplan will look like



• First, we will define the width and height of the core



• First, we will define the width and height of the core

• Then, we will define locations of pre-placed cells


Core


H

Die

Core

W

Block a

Die

Core


Block a Block b

Die

Core


Block a Block b

Block c

Die

Core


Block a Block b
Pre-placed
Cells
Block c

Die

Core


Block a Block b
Pre-placed
Cells
Block c
H

Die

Core

W

Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)

Empfohlen

Empfohlen

Weitere ähnliche Inhalte

Kürzlich hochgeladen

Kürzlich hochgeladen (20)

Empfohlen

Empfohlen (20)

Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)