1. POLITECNICO DI MILANO
Reconfigurable Computing
Italian Meeting
19 December 2008
Room S01, Politecnico di Milano - Milan (Italy)
Sponsored by:
Roma
The Programmable Solutions Company Advanced DSP Group of Atmel Corporation
With the technical support IEEE Computational
of the Italian Chapters of: Intelligence Society

2. Agenda
09.30 – 9.45 Welcome
D. Sciuto (Politecnico di Milano)
09.45 - 11.30 Session 1: Trends
Session chair: V. Rana (Politecnico di Milano)
11.30 – 11.45 Coffee Break
11.45 – 13.15 Session 2: The hArtes European project
Session chair: V. Rana (Politecnico di Milano)
13.15 – 14.15 Lunch
14.15 – 15.30 Session 3: Applicative scenarios
Session chair: F. Cancarè (Politecnico di Milano)
15.30 – 15.45 Coffee Break
15.45 – 17.30 Session 4: The High Level Reconfiguration project description
Session chair: F. Redaelli (Politecnico di Milano)
17.30 - 17.45 Concluding session
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3. Session 1: Trends
Altera FPGA strategy for a reconfigurable approach in industry
application
Speaker: A. Montanaro (ALTERA)
Slide
A Multi-Core Signal Processor for Heterogeneous Reconfigurable
Computing
Speaker: F. Campi (STMicroelectronics)
Slide
Janus: FPGA Based System for Scientific Computing
Speaker: F. Mantovani (Università di Ferrara)
Slide
Future Challenge
Speaker: M Corvo (Mindway )
Slide
3

4. Coffee Break (15’)
Next...
Session 2: The hArtes European project
Session chair: V. Rana (Politecnico di Milano)
4

5. Session 2: The hArtes European project
B2B with minimum TRIMM time. Un obiettivo
ambizioso, ma realizzabile
Speaker: R. Nutricato (Atmel Roma)
Slide
PandA: a framework for task partitioning of
reconfigurable MPSoCs architectures
Speaker: F. Ferrandi (Politecnico di Milano)
Slide
The hardware application platform of the hArtes
project
Speaker: G. Marchiori (Università di Ferrara)
Slide
5

6. Lunch (60’)
Next
14.15 – 15.30 Session 3: Applicative scenarios
Session chair: F. Cancarè (Politecnico di Milano)
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7. Session 3: Applicative scenarios
Evolvable Hardware: past, present and future
Speaker: F. Cancarè (Politecnico di Milano)
Slide
Energy Efficient Coarse-Grain Reconfigurable Array for
Accelerating Digital Signal Processing
Speaker: M. Lanuzza (Università della Calabria)
Slide
Coordinated Management of Hardware and Software
Self-adaptivity
Speaker: A. V. Taddeo (ALaRI)
Slide
7

8. Coffee Break (15’)
Next
Session 4: The High Level Reconfiguration project
description
Session chair: F. Redaelli (Politecnico di Milano)
Concluding session
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9. Session 4: The High Level
Reconfiguration project description
HLR overview
Speaker: F. Redaelli (Politecnico di Milano)
Slide
Core Identification for Reconfigurable Systems driven by Specification
Self-Similarity
Speakers: M. Redaelli (Politecnico di Milano) and R. Cordone
(Università degli Studi di Milano)
Slide
Task Scheduling Techniques on Dynamically Reconfigurable Systems
Speakers: R. Cordone (Università degli Studi di Milano) and F.
Redaelli (Politecnico di Milano)
Slide
Runtime core relocation management for self dynamically reconfigurable
architectures
Speakers: M. Morandi (Politecnico di Milano) and M. Novati
(Politecnico di Milano)
Slide
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10. See you in 2009!
Merry Christmas and
a happy and successful 2009!
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