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Webinar: Practical DDR Testing for Compliance, Validation and Debug

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Join Teledyne LeCroy for this free webinar as we first cover the basics of a DDR interface with a focus on physical-layer test challenges and solutions to common problems. We will then outline the general procedures and considerations for compliance, debug and validation test scenarios. Finally, case studies will illustrate how to apply sophisticated test tools to solve real-life problems.

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Webinar: Practical DDR Testing for Compliance, Validation and Debug

  1. 1. Practical DDR testing for compliance, validation and debug Patrick Connally patrick.connally@teledyne.com
  2. 2. Agenda  Basics of DDR testing  Basics of a DDR interface  Types of testing  Signals of interest  Common DDR test challenges  Signal access  Burst separation  Preparing for physical layer testing  Choosing test equipment  Optimizing oscilloscope setup  DDR compliance testing  Compliance testing background  The compliance testing process  DDR validation and debug  Case study – tracking down a potential signal fidelity issue 2
  3. 3. Basics of DDR testing 3
  4. 4. Basics of a DDR interface  Each DRAM chip transfers data to/from the controller via several data lines, accompanied by a strobe  Since data can flow both from the controller to the DRAM (write operation) and from the DRAM to the controller (read operation), these lines are bi- directional 4 Strobe + Data DRAM chip Controller
  5. 5. Basics of a DDR interface  Common clock, command and address lines are used for all DRAM chips  Since they control the operation of the interface, they are unidirectional (controller-to- DRAM)  The layout shown here is the “fly-by” topology used from DDR3 onwards 5 Strobe + Data Clock, Command, Address DRAM chip Controller
  6. 6. Three types of physical-layer test  Compliance: “Do the device’s output signals comply to the JEDEC specification?”  Validation: “Do the devices interact correctly within the system environment?”  Debug: “Why isn’t my device/system behaving correctly?” 6
  7. 7. Which signals are important?  In physical layer compliance testing and validation, the fastest signals are the most critical:  Clock (CK)  Strobe (DQS)  Data (DQn)  These signals need to be analyzed as analog waveforms to fully characterize their signal fidelity  While there will be many Data lines in an interface, testing them all can be time-consuming  Often, board-level simulation is used to find the expected “worst-case” data lines and test only those 7 Strobe Data Clock
  8. 8. Which signals are important?  The command bus controls the operation of the interface, and indicates the desired activity on the high-speed signals  Knowing the logic state of the command bus signals in a time-correlated way to the analog behavior of the high-speed CK, DQ and DQS signals enables much deeper insight into the system’s behavior  Possible command states vary by DDR protocol, but can include:  Deselect  No operation  Read  Write  Bank Activate  Precharge  Refresh  Mode Register Set 8 Strobe Data CMD bus
  9. 9. A complete analysis system  Analog signals  High-bandwidth oscilloscope  Low-loading differential analog probes 9  Analysis software  Identify bursts  Perform measurement  Digital signals  High-sample- rate digital analyzer  High-bandwidth digital probe
  10. 10. Common DDR test challenges 10
  11. 11. Test challenge 1: accessing signal points  All modern DRAM chips are BGA-packaged, which presents a challenge for testing – how do you access signals which are under the chip?  3 common approaches:  Backside vias  Interposers  DIMM series resistors 11
  12. 12. Access option 1: Backside vias If the BGA balls are accessible on the back side of the board, this is an ideal place to probe the signals of interest  Pros  Usually good signal fidelity (probing near the termination)  Relatively easy access  Cons  Many devices (dual-rank DIMMs, dense embedded systems) don’t allow for this method 12 Backside via probe on single-rank DIMM Backside via probing on “chip-down” system
  13. 13. Access option 2: interposers Interposers install between the DRAM chip and the board, and provide points to connect probes  Pros  Useful in difficult access situations  Generally reasonable signal fidelity  Cons  Additional complexity to install socket correctly  Interposer footprint can cause problems on crowded boards 13
  14. 14. Access option 3: DIMM series resistors For dual-rank (2-sided) DIMMs, the backside vias aren’t accessible – the resistors are a good alternate location  Pros  A relatively accessible probing point when the vias are not accessible  Cons  The distance between the probe and the termination on the DRAM means reflections from the receiver can be a problem 14 Single-ended Data line: resistor to ground Differential Strobe line
  15. 15. Test challenge 2: burst separation  Read and Write bursts share a bus, but must be analyzed separately:  Read bursts originate from the DRAM  Write bursts originate from the controller  Bus is “tri-state” (high-Z at both ends) when neither side is transmitting  It’s critical to be able to identify and isolate the bursts of interest for analysis 15 Idle Write Idle Read
  16. 16. Burst separation option 1: DQ/DQS phase We can use the phase difference between the Data and Strobe to differentiate Reads and Writes  Pros  Identification is simple and requires only the signals being tested  Cons  Signals with lots of noise, reflections, or slow rise/fall times can make phase measurements, and hence burst separation, unreliable 5/11/2017 18 Write Read Clean signals make phase-based separation easy Reflections can make DQ/DQS phase relationship unclear
  17. 17. Burst separation option 2: Command bus Acquiring or triggering on the command bus removes any uncertainty about the coming burst type  Pros  Very reliable separation  Insight into command bus activity and relationship to DQS/DQ  Cons  Requirement to probe several extra signals 19
  18. 18. Preparing for DDR physical-layer testing 20
  19. 19. System bandwidth  Testing DDR systems always requires the use of probes, so we should look at the scope and probes as a complete acquisition system  DDR interfaces have very fast slew rates relative to their data transfer (baud) rates  In order to characterize the system with acceptable rise-time accuracy, a relatively high-bandwidth oscilloscope and probes are required 21 DDR3 slew rate specification
  20. 20. Recommended equipment for common DDR variants 22
  21. 21. Probe loading  Probe loading gets blamed for a lot of observed issues  In our experience, signal fidelity issues can almost always be traced to the signal path within the device  Probes with insufficiently low loading are much more likely to cause functional failures in devices 23 Teledyne LeCroy WaveLink Dxx30 differential probes have ideal characteristics for testing higher-rate DDR systems
  22. 22. Probe mechanical connection  Solder-in probe tips are used in the vast majority of DDR testing applications  Most critical considerations tend to be:  Small physical size - typically many signals need to be probed  Physical flexibility reduces torque on delicate solder connections when probe amplifier is moved  Measurement flexibility – doing several jobs with one tip reduces test setup complexity 24 Teledyne LeCroy QuickLink probe tips are low-cost, high bandwidth, 9-inch flexible tips that can be interchanged between analog and digital instruments
  23. 23. Preparing to measure: deskewing  Deskewing is critically important in all applications where probes are used for timing measurements, but even more so in a DDR environment  The importance of the DQ/DQS phase in many measurements makes them particularly sensitive to skew issues 25 Deskewing probes using the oscilloscope’s fast edge output These probing points are close together, so the same reference plane can be used
  24. 24. Preparing to measure: maximize dynamic range 26 Signals are using ~50% of the grid This reduces Signal-to-Noise ratio by about 6dB Signal is “clipping” – it could be overdriving the oscilloscope’s front-end What not to do.
  25. 25. Preparing to measure: maximize dynamic range 5/11/2017 27 Each signal has its own grid Maximizes dynamic range without sacrificing viewability Each signal occupies about 6 vertical divisions Good practice
  26. 26. Preparing to measure: checking signal levels  Make sure the signal levels appear as specified for the DDR variant you’re working on  Many automated measurements rely on “the basics” being correct  If they don’t, it might be…  A probing problem (wrong reference, cross-probed, inverted)  A device/system problem (Wrong Vdd, wrong Vref) 28 DDR2 LPDDR2 DDR3 LPDDR3 DDR4 LPDDR4 Vpp Single-ended 0 to 1.8 V 0 to 1.2 V 0 to 1.5 V 0 to 1.2 V 0 to 1.2 V Differential -1.8 to 1.8 V -1.2 to 1.2 V -1.5 to 1.5 V -1.2 to 1.2 V -1.2 to 1.2 V Vref (reference voltage) Single-ended 0.9 V 0.6 V 0.75 V 0.6 V 0.6 V Differential 0 V 0 V 0 V 0 V 0 V
  27. 27. DDR Compliance Testing 29
  28. 28. Why do compliance testing? DRAM and/or controller vendors  Must be able to prove to their customers that their devices abide by the standards as defined by JEDEC  There is no formal certification process for DDR “compliance” – manufacturers essentially self-certify  This makes documentation of test procedures and results critical 30 System designers  No explicit need to prove JEDEC compliance to “downstream” customers  Validation of device functionality is much more critical  System layout is often not optimal for signal fidelity testing  But a compliance report is often desirable as concrete verification that design goals have been met
  29. 29. Probing for compliance testing  Specification assumes the signal is probed directly at the balls of the DRAM BGA  This is not always feasible  Access issues  Need to connect twice as many probes 31 CK DQS DQ Add/Ctrl DDR4 Differential Differential Single-Ended Single-Ended DDR3 Differential Differential Single-Ended Single-Ended LPDDR3 Differential Differential Single-Ended Single-Ended DDR2 Differential Differential or Single-Ended Single-Ended Single-Ended LPDDR2 Differential Differential Single-Ended Single-Ended
  30. 30. Compliance testing is complicated! Fully covering the JEDEC standard for any given DDR variant means doing a lot of tests. Automated compliance test software options for the oscilloscope…  Make testing less time-consuming  Reduce errors due to measurement complexity  Increase repeatability  Generate test reports automatically 32 Test coverage of Teledyne LeCroy QPHY-DDR4 automated compliance test option
  31. 31. Step 1: acquire signals  Lots of data makes for more reliable, repeatable results  We take a long acquisition to ensure good statistical confidence in the measurements  High traffic density during testing is important  Run memtest or another script to induce lots of traffic 33 Clock Strobe Data Address
  32. 32. Step 2: separate read/write bursts  Read and Write bursts must be analyzed separately  They come from different transmitters  Some of their parameters are defined differently  For systems with high-quality signals and/or using low speed grades, DQ/DQS phase produces good separation results  At higher rates or in low-signal-quality situations, phase measurement can become unreliable  In these situations, we recommend acquiring the CMD bus to ensure reliable burst separation 34
  33. 33. Step 3: perform measurements 35  Measurements are performed on all bursts in the acquired waveform  Results, statistics and screenshots are retained for report generation  Possible reasons for problems/failures:  Signal quality issues due to system/board signal paths  Probes not connected correctly  Burst separation problems (possibly due to the above)  The device does not meet the specification
  34. 34. Step 4: Generate eye diagrams  Eye diagrams are only required for compliance testing in DDR4 and LPDDR4 variants  But they are an incredibly useful tool for visualizing overall signal quality, so they form part of the automated test package for all variants 36
  35. 35. Step 4: Generate eye diagrams 37 Write burst Read burst Write burst eye pattern Read burst eye pattern
  36. 36. Step 5: Generate report  Reports contain:  A summary of the test results, including pass/fail status  More details of each individual test  Screenshots of the tests being performed 38
  37. 37. DDR Validation and Debug A case study using Teledyne LeCroy’s DDR Debug Toolkit 39
  38. 38. The complete system view 40 Analog probes: DQ/DQS/CK waveforms for waveshape analysis and eye diagrams Digital Acquisition: For better burst separation and insight into command bus behavior
  39. 39. What signals are we probing and how?  Strobe (DQS): Analog C2  Data (DQn): Analog C3  Command bus:  Chip Select (CS): Digital D0  Write Enable (WE): Digital D1  Row Address Select (RAS): Digital D2  Column Address Select (CAS): Digital D3  Clock (CK): Digital D4 or Analog C1  QuickLink probe tips can be used for both digital and analog signals 42
  40. 40. Deskew  Make sure to deskew all analog and digital signals to the same timing reference  Teledyne LeCroy oscilloscopes have a Fast Edge output to make deskewing easy. 43
  41. 41. First look at the analog signals  Looking at just the DQ and DQS analog signals, we can see some strange non- monotonicities on the edges  DDR Debug Toolkit is the ideal tool for tracking down this kind of issue 44
  42. 42. Bus view  Annotating bus states and corresponding DQ/DQS activity makes system analysis easier 45
  43. 43. Bus view  The bus view also gives a direct reference from the system behavior to the JEDEC spec 46
  44. 44. Look closer with triggers  We can use the CMD bus to trigger on an event of interest  Let’s trigger on Read bursts  They all show non- monotonous edges 47
  45. 45. Look closer with triggers  Triggering on Write bursts doesn’t show any evidence of bad edges  Will the bad Read edges affect our eye diagrams? 48
  46. 46. Eye diagrams and burst separation  The non- monotonous edges on the Read bursts are hindering the phase-based burst separation approach  It’s hard to measure phase with a discontinuity right at the Vref crossing point  We can see some Reads end up in with the Writes as a result 49
  47. 47. Eye diagrams and burst separation  Using the CMD bus to separate Reads and Writes leads to “clean” eye diagrams  But that non- monotonicity will cause problems for other measurements  Is it a real phenomenon? 50
  48. 48. Where’s the signal being probed? 5/11/2017 51 PCB DRAM Memory Controller
  49. 49. So what’s going on here? DRAM Controller Z0 = 50Ω RT >> 50Ω VA VB VA VB T1 T2 T3
  50. 50. Measure the propagation delay  We can use the signal itself as a TDR pulse  Here, the round-trip delay is approximately 680ps 5/11/2017 53
  51. 51. Now we have a simple model 5/11/2017 54 Z0 = 50Ω RT >> 50Ω VA VB TD = 340ps DRAM Controller
  52. 52. This gives us “virtually probed” read bursts  The probing point has been “moved” to the termination using Virtual Probe technology, eliminating the reflections 55 Original Virtual
  53. 53. Make sure you pick the correct probe point 5/11/2017 56 PCB DRAM Memory Controller You should still analyze Write bursts from here Read burst analysis should come from here “Real” probe Virtual probe
  54. 54. The final eye diagram view  When we view each signal from the correct probing point, both Read and Write bursts look good 57
  55. 55. Questions? patrick.connally@teledyne.com 58

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