3. FPGAによる高速化が注目されています
ソーティング – 主要な計算カーネル
2
[1] Rene Mueller et al, Sorting Networks on FPGAs, The VLDB Journal 2012
[2] Ratnayake, K et al,
An FPGA Architecture of Stable-Sorting on a Large Data Volume : Application to Video Signals,
CISS 2007
[3] Martinez, J et al,
An FPGA-based parallel sorting architecture for the Burrows Wheeler transform
ReConFig 2005
データベース処理[1] 画像処理[2] データ圧縮[3]
DATA
8. 複数のソート済みデータ列を1つにマージするデータパス
図は 4-way Merge Sorter Tree
ソート対象のデータ列が入力数より多い場合は複数回通す必要
基本的なアーキテクチャ – Merge Sorter Tree
7
参考: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting.
(Dirk Koch and Jim Torresen, FPGA ’11,)
>
>
> > ソートセル
FIFO
入力レーン
=
way
58. Merge Sorter Tree
例: data = {8, 9, 3, 5, 1, 3, 2, 2}
out = {}
81
参考: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting.
(Dirk Koch and Jim Torresen, FPGA ’11,)
>
>
>
9 8
5 3
3 1
2 2
Unit: ソート済みデータ列
59. Merge Sorter Tree
data = {8, 9, 3, 5, 1, 3, 2, 2}
out = {}
82
参考: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting.
(Dirk Koch and Jim Torresen, FPGA ’11,)
>
>
>
9 8
5 3
3 1
2 2
3
1
60. Merge Sorter Tree
data = {8, 9, 3, 5, 1, 3, 2, 2}
out = {}
83
参考: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting.
(Dirk Koch and Jim Torresen, FPGA ’11,)
>
>
>
9 8
5
3
2 2
3
1
5
2
1
61. Merge Sorter Tree
data = {8, 9, 3, 5, 1, 3, 2, 2}
out = {1}
84
参考: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting.
(Dirk Koch and Jim Torresen, FPGA ’11,)
>
>
>
9 8
5
3
2
3
2
5
2
2
62. Merge Sorter Tree
data = {8, 9, 3, 5, 1, 3, 2, 2}
out = {1,2}
85
参考: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting.
(Dirk Koch and Jim Torresen, FPGA ’11,)
>
>
>
9 8
5
3
3
2
5
3
2
63. Merge Sorter Tree
data = {8, 9, 3, 5, 1, 3, 2, 2}
out = {1,2,2}
86
参考: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting.
(Dirk Koch and Jim Torresen, FPGA ’11,)
>
>
>
9 8
5
3
3
5
3
64. Merge Sorter Tree
data = {8, 9, 3, 5, 1, 3, 2, 2}
out = {1,2,2,3}
87
参考: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting.
(Dirk Koch and Jim Torresen, FPGA ’11,)
>
>
>
9 8
5
3
8
3
65. Merge Sorter Tree
data = {8, 9, 3, 5, 1, 3, 2, 2}
out = {1,2,2,3,3}
88
参考: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting.
(Dirk Koch and Jim Torresen, FPGA ’11,)
>
>
>
9 8
5
8
5
66. Merge Sorter Tree
data = {8, 9, 3, 5, 1, 3, 2, 2}
out = {1,2,2,3,3,5,8,9}
89
参考: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting.
(Dirk Koch and Jim Torresen, FPGA ’11,)
>
>
>