DRCs

C1:
• Category: Clock
• Default Handling: Error
• A scan or non-scan cell must not capture data when all specified clocks are set to their off
states
• One common root cause of these C1 violations is a set/reset pin not defined as a clock. You
can define a set/reset pin as a clock to fix the problem and avoid ATPG performance impact.
• Effect on Testability :
Failure to satisfy this rule can result in unstable scan and non-scan cell values going
into or coming out of load_unload, or between cycles. This can result in lower test coverage.

C1:
Possible Resolutions
• If your debugging effort shows an offending clock’s off
state is incorrect, use the add_clocks command to
redefine the clock with the correct off state.
• If the off state is correct, the problem typically is due to
an indeterminate value (X) in related logic that causes
the clock’s value at a scan cell to be X. You can fix
these by using the add_input_constraints command to
constrain a primary input pin to a value that removes
the X:
add_input_constraints -c0 EN
add_input_constraints –c1 EN

C2:
• Default Handling: Warning
• Each clock must have a structural path to the clock port of at least one memory element. The
application performs this check by a backward tracing from the clock port, SET/RESET port, and
read/write enables of all memory elements toward primary inputs. The rule violation occurs if a clock
primary input cannot be reached.
• Clock ‘CLK’ cannot reach the clock port of any memory element
• Defining a pin to be a clock, when it does not behave as a clock, is the most usual cause of this error
condition
• Failure to satisfy this rule indicates a defined clock cannot capture data, thus reducing test coverage.
C2 Rule Violation Example:
If you run rules checking on this design, you get a
C2 rules violation because while the CK17 signal
appears to be a clock (due to its name), it cannot
be reached from the clock port or SET/RESET
ports of the flip-flop. To fix this problem, add the
command:
delete_clocks CK17
Then, you must re-run checks.

C7:
• Default Handling: Warning
• The rule violation occurs when a clock input of a scan cell always remains off.
• Failure to satisfy this rule indicates a scan cell clock input cannot capture data, resulting in some
loss of test coverage.
• Message:
Clock input I of N (G) cannot capture data with a single clock on. (C7-1)
C7 Rule Violation Example
This design constrains the SCAN_MODE signal to a constant 0
during ATPG. This constraint prevents the first flip-flop from
ever being clocked, and from ever capturing data. To fix this
problem, delete the pin constraint:
delete_input_constraints -all

C9:
• Default Handling: Warning
• The rule violation occurs on a clock pin when a primary output is in both the clock cone and the
effect cone.
• Failure to satisfy this rule may result in a small loss in test coverage.
• Message:
PO P path from clock C is gated by scan cell that uses same clock
• C9 violation can result in reduced coverage because it may introduce sequential effects into the
generated clock patterns
C9 Rule Violation Example
The tool setup for the clocks is:
add_clocks 0 func_clk
In this case, the violation is at the out1 line. The
func_clk signal can affect the data of the flip-flop
and the gate at the output of the scan cell.
An acceptable solution is to accept this warning,
or turn it off with the command:
set_drc_handling c9 ignore

C23:
• Default Handling: Warning
• This rule checks if a scan cell cannot capture fault effects
because its clock port is constrained to 0 or 1.

T12
• Category: Trace
• Contexts Supported: dft -scan, dft -test_points, patterns -scan, patterns -
scan_diagnosis
• Default Handling: Warning
• When the handling is set to other than error, the tool automatically makes
the necessary MASTER unobservable to prevent a potential simulation
mismatch. This applies only to the MASTER of the scan cell containing a
SLAVE. The scan cell without a SLAVE retains its original observability. Due
to the loss of observability on some MASTERs, test coverage may be
reduced. To correct this violation, you can define a master_observe
procedure to propagate the MASTER value to the SLAVE.

W17
• Category: Timing
• Contexts Supported: dft -scan, dft -test_points, patterns -scan, patterns -
scan_diagnosis
• Default Handling: Error (cannot be changed with the set_drc_handling
command)
• it is important that the timeplates used in a clock_po procedure do not
pulse the clock pins, but only force them. If this is not corrected before
patterns are saved, the Vector Interfaces code places X values on the
output pins for the clock_po procedure and fault coverage decreases.
• T specifies which timeplate has the clock pulses. To correct this, make
sure you define a different timeplate that does not have clock pulses and
use this in the clock_po procedure.

A6
• Category: RAM
• Contexts Supported: dft -scan, dft -test_points, patterns -scan, patterns -
scan_diagnosis
• Default Handling: Warning
• The rule violation occurs if any write, set, or reset input of any RAM, or a read
input of a data_hold RAM is not off.Failure to satisfy this rule for write inputs
results in the RAM being unavailable to hold its contents during scan operation,
which may cause a loss in test coverage.
• When an error condition occurs, you can access the simulated values by setting
the gate reporting to error_pattern and using the report_gates command for the
gate ID number displayed in the error message. This identifies the input that is not
held off, and by tracing back from this input, you can identify how to correct the
problem. The usual cause of this error condition is not defining all write or read
control lines, or defining the wrong off-state.

A10
• Category: RAM
• Contexts Supported: dft -scan, dft -test_points, patterns -scan_diagnosis
• Default Handling: Warning
• The usual cause of this error condition is not forcing the primary inputs, or not
initializing the state elements, that control the RAM’s set or reset port to an
appropriate value.
• When an error condition occurs, you can access the simulated values by setting the
gate reporting to error_pattern and using the report_gates command for the gate
ID number displayed in the error message. This identifies the set or reset port that
is not held off during simulation of a procedure, and by tracing back from this
input, you can identify how to correct the problem.
• When the A10 or A11 rule is violated, the tool treats the RAM as TIEX, which may
reduce fault coverage

A11
• Category: RAM
• Contexts Supported: dft -scan, dft -test_points, patterns -
scan_diagnosis
• Default Handling: Warning
• When an error condition occurs, you can access the simulated values
by setting the gate reporting to error_pattern and using the
report_gates command for the gate ID number displayed in the error
message. This identifies the set or reset port that is not held off
during capture, and by tracing back from this input, you can identify
how to correct the problem. The usual cause of this error condition is
not constraining the primary inputs or the state elements that control
the RAM’s set or reset port.