The document discusses software driven verification using Xilinx's xsim simulator. It describes using the Xilinx Simulator Interface (XSI) which allows a C/C++ program to act as a testbench for an HDL design in xsim. It provides details on how to use XSI functions like getting port numbers and values, running simulation, and controlling simulation from C++. It also discusses calling XSI functions through dynamic linking and using SystemVerilog DPI to directly access the DUT from C++.

1. Xilinxのxsimで
Software Driven Verification雑談会
2022.05.22
@Vengineer
Xilinx の xsim で
Software Driven Verification

2. ブログ (2007年～) : Vengineerの戯言
https://vengineer.hatenablog.com/
SlideShare :
https://www.slideshare.net/ssuser479fa3
Twitter (2009年～) :
＠Vengineer
Software Driven Verifaction

3. ● Software Driven Verification
○ UVM (Universal Verification Methodology) : SystemVerilog
○ SystemVerilog : BFM + DPI (export task)
● Xilinx Simulator Interface
● Xilinx Simulator Interface での Software Driven Verification
○ XSI
○ XSI + SystemVerilog DPI
● おわりに
発表内容

4. Software Driven Verification
● ソフトウェア(プログラム)を使って、ハードウェア(RTL等)を検証する
DUT (Design under Test)
RTL等で記述
Model
Driver/Checker/Monitor
Test Program
Top Testbench

5. SystemVerilogでは？
● UVM (Universal Verification Methodology) : UVM 2020-1.1
DUT (Design under Test)
SystemVerilog
Model
SystemVerilog
Test Program
SystemVerilog
Top Testbench
(SystemVerilog)
商用HDLシミュレータ、xsimでも利用可能

6. SystemVerilogでは？
● BFM + DPI (export task)
○ Xilinx xsim では、時間が進む task はサポートしていない
DUT (Design under Test)
SystemVerilog
Model
SystemVerilog
Test Program
C/C++
Top Testbench
(SystemVerilog)
DPI (export task)

7. Xilinx Simulator Interface
The Xilinx® Simulator Interface (XSI) is a C/C++ application
programming interface (API) to the Xilinx Vivado simulator (xsim) that
enables a C/C++ program to serve as the test bench for a HDL design.
Using XSI, the C/C++ program controls the activity of the Vivado
simulator which hosts the HDL design.
● Verilator の テストベンチ側を C++ で書くのと同じ？

8. Xilinx Simulator Interface
● Simulation Engine + Design + C/C++ (Testbench + Test Program)
DUT (Design under Test)
SystemVerilog
Model
SystemVerilog
Test Program
C/C++
Top Testbench
(C/C++)
Design
Simulation
Engine

9. XSIでのシミュレーション制御
The C/C++ program controls the simulation in the following methods:
● Setting the values of the top-level input ports of the HDL design
● Instructing the Vivado simulator to run the simulation for a certain
amount of simulation time
● Additionally, the C/C++ program can read the values of the top-level
output ports of the HDL design.

10. XSIのステップ
Perform the following steps to use XSI in your C/C++ program:
1. Prepare the XSI API functions to be called through dynamic linking
2. Write your C/C++ test bench code using the API functions
3. Compile and link your C/C++ program
4. Package the Vivado simulator and the HDL design together into a
shared library

11. XSIをDynamic Linkingで呼び出す
Xilinx recommends the usage of dynamic linking for indirectly calling the
XSI functions.
While this technique involves more steps than simply calling XSI
functions directly, dynamic linking allows you to keep the compilation of
your HDL design independent of the compilation of your C/C++
program.
You can compile and load your HDL design at any time, even while your
C/C++ program continues to run.

12. XSIをDynamic Linkingで呼び出す
To call a function through dynamic linking requires your program to
perform the following steps:
1. Open the shared library containing the function.
2. Look up the function by name to get a pointer to the function.
3. Call the function using the function pointer.
4. Close the shared library (optional).

13. XSIを使ってシミュレーションをする
To call a function through dynamic linking requires your program to
perform the following steps:
A C/C++ test bench using XSI typically uses the following steps:
1. Open the design.
2. Fetch the IDs of each top-level port.
3. Repeat the following until the simulation is finished:
a. Set values on top-level input ports.
b. Run the simulation for a specific amount of time.
c. Fetch the values of top-level output ports.
4. Close the design.

14. XSI API
● xsi_load で データベースからDesignを取り出す
● xsi_open でシミュレーションのオープン
● xsi_get_port_number でポート名からポート番号を取り出す
● xsi_get_value でポート番号の信号にデータをリード
● xsi_put_value でポート番号の信号にデータをライト
● xsi_trace_all で信号のダンプ
● xsi_run で、シミュレーションを進める
● xsi_get_time でシミュレーション時間を得る
● xsi_restart で、シミュレーションのリセット
● xsi_close で終了

15. XSIを使ってシミュレーションをする
XSI APIを使って、シミュレーション
1. xsi_load & xsi_open
2. xsi_get_port_number
3. 下記を繰り返す
a. xsi_put_value
b. xsi_close
c. xsi_run
4. Close the design.

16. XSIのTop Testbench
● main関数の中には、C++ の bfm しかない
DUT (Memory)
SystemVerilog RTL
Test Program
C/C++
Top Testbench
(C/C++)
C++ Model
int main() {
bfm u_bfm;
u_bfm.main();
return 0;
} ● Read
● Write
Simulation Engine
XSI
BFM

17. module top
(
input logic clk,
input logic reset,
input logic [15:0] addr,
input logic cs,
input logic rw,
input logic [31:0] data_in,
output logic ready,
output logic [31:0] data_out
);
localparam ram_size = (17'h10000>>2);
logic [31:0] ram[ram_size];
enum {STATE_IDLE, STATE_RUN, STATE_DONE} state;
always_ff @(posedge clk) begin
if(reset == 1'b1)
state <= STATE_IDLE;
else if(cs == 1'b1 && state == STATE_IDLE)
state <= STATE_RUN;
else if(cs == 1'b1 && state == STATE_RUN)
state <= STATE_DONE;
else if(cs == 1'b0)
state <= STATE_IDLE;
end
DUT (Memory)
always_ff @(posedge clk) begin
if(reset == 1'b1) begin
data_out <= 32'h0000_0000;
ready <= 1'b0;
end
else if(state == STATE_RUN) begin
if(rw == 1'b1)
data_out <= ram[addr[15:2]];
else
ram[addr[15:2]] <= data_in;
ready <= 1'b1;
end
else begin
data_out <= 32'h0000_0000;
ready <= 1'b0;
end
end
endmodule

18. #include "bfm.h"
int main() {
bfm u_bfm;
u_bfm.main();
return 0;
}
Top Testbench (testbench.cpp)

19. include <cstring>
#include <iostream>
#include "xsi_loader.h"
class bfm {
public:
bfm();
~bfm();
void main();
private:
Xsi::Loader xsi;
BFM (bfm)
// ポート
int clock;
int reset;
int cs;
int rw;
int addr;
int data_in;
int data_out;
int ready;
void write_hi(int sig);
void write_low(int sig);
void wait_hi();
void wait_low();
void wait();
void reset_task();
bool read_ready();
void write_addr(uint32_t data);
void write_data(uint32_t data);
uint32_t read_data();
uint32_t read(uint32_t addr_);
void write(uint32_t addr_, uint32_t data_);
}
$XILINX_VIVADO/examples/xsim/verilog/xsi/counter
xsi_loader.h
xsi_loader.cpp
xsi_shared_lib.h

20. BFM (bfm)
bfm::bfm() :
xsi("xsim.dir/top/xsimk.so", "librdi_simulator_kernel.so")
{
s_xsi_setup_info info;
memset(&info, 0, sizeof(info));
info.logFileName = NULL;
char wdbName[] = "test.wdb";
info.wdbFileName = wdbName;
xsi.open(&info); // open
xsi.trace_all(); // trace
// ポート番号の獲得
clock = xsi.get_port_number("clk");
reset = xsi.get_port_number("reset");
cs = xsi.get_port_number("cs");
rw = xsi.get_port_number("rw");
addr = xsi.get_port_number("addr");
data_in = xsi.get_port_number("data_in");
data_out = xsi.get_port_number("data_out");
ready = xsi.get_port_number("ready");
write_low(cs);
write_low(rw);
write_addr(0x00);
write_data(0x00);
}
xsim.dir/top/xsimk.so => Design
librdi_simulator_kernel.so => Simulation Engine

21. void bfm::main(){
reset_task();
test_main();
cout << "time = " << xsi.get_time() << endl;
}
void bfm::test_main(){
cout << "start test_main" << endl;
write(0x200, 0x12345678);
uint32_t data = read(0x200);
if(data != 0x12345678)
cout << "<<ERR>>, compare error, data = 0x" << hex << data << endl;
cout << "finish test_main" << endl;
}
BFM (bfm)

22. bfm::~bfm(){
xsi.close(); // close
}
// 値のライト
void bfm::write_hi(int sig) {
xsi.put_value(sig, &one_val);
}
void bfm::write_low(int sig) {
xsi.put_value(sig, &zero_val);
}
// 時間を進める
void bfm::wait_hi() {
write_hi(clock);
xsi.run(clock_period_2);
}
BFM (bfm)
void bfm::wait_low() {
write_low(clock);
xsi.run(clock_period_2);
}
void bfm::wait() {
wait_hi();
wait_low();
}
void bfm::reset_task(){
write_hi(reset);
for(int i=0;i<4;i++) {
wait();
}
write_low(reset);
wait();
cout << "done reset" << endl;
}

23. bool bfm::read_ready() {
s_xsi_vlog_logicval val;
xsi.get_value(ready, &val); // 値のリード
cout << "time : " << dec << xsi.get_time() << ", val.aVal(0x" << hex << val.aVal << "), val.bVal(0x" <<
val.bVal << ")" << endl;
return ((val.aVal & 0x1) ? true : false);
}
void bfm::write_addr(uint32_t data) {
s_xsi_vlog_logicval val = {data, 0x0};
cout << "write_addr(0x" << hex << data << ")" << endl;
xsi.put_value(addr, &val); // 値のライト
}
void bfm::write_data(uint32_t data) {
s_xsi_vlog_logicval val = {data, 0x0};
cout << "write_data(0x" << hex << data << ")" << endl;
xsi.put_value(data_in, &val); // 値のライト
}
BFM (bfm)

24. uint32_t bfm::read(uint32_t addr_){
write_hi(cs);
write_hi(rw);
write_addr(addr_);
wait_hi();
wait_low();
while(!read_ready()){
wait();
}
uint32_t data = read_data();
write_low(cs);
write_low(rw);
write_addr(0x0);
wait_hi();
wait_low();
return data;
}
BFM (bfm)
void bfm::write(uint32_t addr_, uint32_t data_){
write_hi(cs);
write_low(rw);
write_addr(addr_);
write_data(data_);
wait_hi();
wait_low();
while(!read_ready()){
wait();
}
write_low(cs);
write_low(rw);
write_addr(0x0);
write_data(0x0);
wait_hi();
wait_low();
}

25. #!/bin/bash
VIVADO_BIN_DIR="$XILINX_VIVADO/bin"
OUT_SIM_SNAPSHOT="top"
XSI_INCLUDE_DIR="$VIVADO_BIN_DIR/../data/xsim/include"
GCC_COMPILER="/usr/bin/g++"
XSIM_ELAB="xelab"
OUT_EXE="run_simulation"
export LD_LIBRARY_PATH="$XILINX_VIVADO/lib/lnx64.o"
run.sh

26. # xelab : Compile the HDL design into a simulatable Shared Library
$XSIM_ELAB work.top -prj top.prj -dll -s $OUT_SIM_SNAPSHOT -debug wave
# Compile the C++ code that interfaces with XSI of ISim
$GCC_COMPILER -I$XSI_INCLUDE_DIR -O3 -c -o xsi_loader.o xsi_loader.cpp
# Compile the program that needs to simulate the HDL design
$GCC_COMPILER -I$XSI_INCLUDE_DIR -O3 -c -o bfm.o bfm.cpp
$GCC_COMPILER -I$XSI_INCLUDE_DIR -O3 -c -o testbench.o testbench.cpp
# make executable
$GCC_COMPILER -o $OUT_EXE bfm.o testbench.o xsi_loader.o -ldl -lrt
# Run the program (export LD_LIBRARY_PATH="$XILINX_VIVADO/lib/lnx64.o")
./$OUT_EXE
run.sh

27. sv work top.v
# List other design files here
sv => SystemVerilog
work => library
top.prj

28. Xilinx xsim : XSI
● Test Program を別ファイルにして、いろいろなテストができる
DUT (Memory)
SystemVerilog RTL
Test Program
SystemC
Top Testbench
(C/C++)
● Read
● Write
Test Program
SystemC
Test Program
SystemC
Test Program
SystemC
Test Program
SystemC
Test Program
SystemC
Test Program
SystemC
Test Program
SystemC
Test Program
C/C++
Simulation Engine
XSI
BFM

29. testbench.cpp
#include "bfm.h"
int main() {
bfm u_bfm;
u_bfm.main();
return 0;
}
bfm.cpp (bfm.hpp)
void bfm::main(){
reset_task();
test_main();
}
BFM (bfm) + Test Program (test1.cpp)
void bfm::test_main(){
cout << "start test_main" << endl;
write(0x200, 0x12345678);
uint32_t data = read(0x200);
if(data != 0x12345678)
cout << "<<ERR>>, compare error, data = 0x"
<< hex << data << endl;
cout << "finish test_main" << endl;
}

30. Xilinx xsim : XSI + SystemVerilog DPI
● SystemVerilogのDPIを使うと、DUTの中に直接アクセスできる
DUT (Memory)
SystemVerilog RTL
Simulation Engine
XSI
Test Program
SystemC
Top Testbench
(C/C++)
● Read
● Write
Test Program
SystemC
Test Program
SystemC
Test Program
SystemC
Test Program
SystemC
Test Program
SystemC
Test Program
SystemC
Test Program
SystemC
Test Program
C/C++
SystemVerilog DPI
BFM

31. ● Software Driven Verification
○ UVM (Universal Verification Methodology) : SystemVerilog
○ SystemVerilog : BFM + DPI (export task)
● Xilinx Simulator Interface
● Xilinx Simulator Interface での Software Driven Verification
○ XSI
○ XSI + SystemVerilog DPI
おわりに

32. ありがとうございました
＠Vengineer
是非、
Software Driven Verification
をやってみてください