testing for pipelined adc

1. Testing of Pipelined
Analog to Digital Converter
BY
S.STINISHITH

2. ABSTRACT
• Analog to Digital converters are some of the most
commonly used mixed-signal circuits nowadays.
• Testing such circuits has recently become
extremely important.
• So , we are using a low-cost test is developed for
a one-stage Pipelined Analog-to-Digital Converter
(P ADC).
• This circuit consists of one operational amplifier,
one comparator, five transmission gates and two
capacitors and is based on a 90 nm CMOS
technology.

3. INTRODUCTION
• The need for mixed analog and digital signal
integrated circuits has increased. The most
commonly used mixed signal devices are
Analog-to-Digital Converters (ADCs) and
Digital-to-Analog Converters (DACs).
• Pipelined ADCs (P ADC) have been usually
favoured for high speed and reasonable
resolution applications (e.g., WLAN data
channels,ADSL data channels, HDTV)

4. • The specifications of ADCs can be divided into
static
1. Static Parameters and
2.Dynamic parameters.
• The static parameters of ADCs may include
accuracy, resolution, differential nonlinearity
(DNL), and integral nonlinearity (INL); while the
• dynamic parameters may include signal to noise
and distortion ratio (SNDR), effective number of
bits (ENOB), and total harmonic distortion
(THO).

5. • The pipe lined analog to digital converter is appropriate for
high speed applications with reasonable resolution. The
main advantage of the PADC appears in a linear scaling of
power and area with resolution.
• Fig. shows the architecture of the pipelined analog to digital
converter. For an N-bit PADC, there are N-I similar stages
and a last stage that consists of a simple flash ADC.
• Each of the N-I stages consists of a sub-ADC and a
multiplying DAC (MDAC). The MDAC consists of a sub
DAC a subtractor and an amplifier. [n the N-I stages, the
analog input signal is digitized by the sub-ADC, producing
the digital output for this stage.

6. ONE STAGE PIPELINE

7. Pipelined analog to digital converter

8. • The PADC provides time efficiency since each
stage processes its input concurrently. Hence,
at the same moment, each stage is processing
a different sample.

9. It consist of two parts:
1.Sub ADC
2.MDAC (multiplier DAC)

10. Sub ADC: The sub ADC is simply a comparator. Its
positive terminal is connected to the analog input,while its negative
terminal is connected to the decision level Vrefl2. The output of the
comparator is KVref,
where K= 1 if Yin > Vrefl2 and
K=O if Yin <Vrefl2.
• Multiplying DAC (MDAC): The MDAC consists of a sub-DAC,
a subtractor and an amplifier. The MDAC
is realized by a switched capacitor circuit .
This switched capacitor circuit consists of an operational
amplifier (Op Amp), two capacitors with equal values, and five
transmission gates that realize the switches. Three switches (SI, S2,
S3) are controlled by¢! and the remaining two switches (S4 and S5)
are controlled by ¢2 ' where ¢l and ¢2 are non-overlapped clocks.

11. • In the sampling mode (during PHI 1), the total charge
stored on C1 and C2 is equal to:
where Cin is the input capacitance of the Op Amp and VX
is the voltage at the inverting input of the op amp.
• In the amplification mode (during ¢2)' the sub-ADC
is clocked
The total charge existing on C1 ,C2 and Cx in this mode is
given by:

12. Since, conservation of charge requires that Qamplification =
Qsampling , the following equation can be obtained:
and since C1 = C2, therefore
where K= I if Vin> Vref/2 and K=O if Vin < Vref/2.

13. Testing
• Mainly research focus on two types of faults in
Testing ADC
they are
1)Catastrophic faults.
2)Parametric faults.
• parametric faults include the reduced open loop gain, the
increased input offset voltage and the reduced output voltage
swing. On the other hand,
• catastrophic faults consist of the
output of the op amp stuck-at-VDD, the output of the op amp
stuck-at-Vss. the output of the op amp stuck-at-Vpos and the
output of the op amp stuck-at-Vneg

14. • capacitors, the fault model is an open fault, which is
modeled by a large resistance in series with the capacitor, and
a short fault, which is modeled by a small resistance across the
Capacitor
• switch realized by a transmission gate, the fault model
consists of stuck-on faults which are modeled by
replacing the faulty switch by the On resistance of the switch
RoN

15. stuck-open faults by substituting the faultyswitch by the Off
resistance of the switch RoFF
• shorted switch which is modeled as a resistive impedance
Rshort between its input and output terminals .

17. Test generation
• The number of test inputs is related to the input range as
follows: Since the input is compared to (Vref / 2) hence, the
range of inputs can be divided into 2 regions:
region A: Vin < 0.5V and
region B: Vin > 0.5V.
Since the range of inputs is divided into 2 regions, then at least 2
test inputs are needed. Let us assume a test input T1 in range A
and a test input T2 in range B. if both T1 and T2 can generate
each other, then, they will follow the equations:
• T1 = 2T2-Vref
• T2 = 2T1

18. The following values are obtained: T1 = 1/3 V and T2 = 2/3 V. For
example, if the input voltage to stage 1 is Vin = T1 = 1/3V
(rangeA), then the analog and digital outputs of stage 1 will be
T2= 2/3 V and ‘0’ respectively. In addition, if the input of stage 2
is Vin = T2 = 2/3 V, then the analog and digital outputs of stage 2
will be T1 = 1/3 V and ‘1’ respectively. It is obvious from that
both T1 and T2 can reach the input of any stage of the N-stage. In
case of starting with T1, the digital output pattern will be
P1=‘0101……’.

19. In case of starting with T2, the digital output pattern will be
P2=‘1010…..’

20. Simulation setup
• capacitors are of equal values C1 = C2 = 1pF. The value
of the two capacitors was chosen to be 1pF since large
capacitors consume a very large area and slow down
the circuit .
• The macromodel of the operational amplifier used has
the following specifications: Rin =50Mohm,
Rout=100ohm, the open loop gain A=10^3, its positive
supply voltage is 1 V and its negative supply voltage is
connected to the ground The switches are implemented
by transmission gates. The transmission gates are
implemented in 90nm MOS model.

21. • where RDSN, RDSP, and RoNC are the resistance of the NMOS
transistor, the resistance of the PMOS transistor and the total
resistance of the transmission gate respectively. The value
of RON is found by simulation to be 870 0hm, while the value of
ROFF is 80M Ohm as in [25]. In addition, the value of Rshort is
assumed to be equal to RON of the switch
All switches have the same ON and OFF resistances.
The switch resistance can be obtained from the
following formulas:

23. Faults detected using T1 and observing D1, D2
Faults detected using T1 and observing D1, D2,
and D3

24. Faults detected using T1 and observing D1, D2, D3,
and D4
Similarly for T2

25. THANK YOU