1. A 500-MHz Low-Voltage Programmable Gain
Amplifier for HD Video in 65-nm CMOS
Syed Ahmed Aamir and J Jacob Wikner
Department of Electrical Engineering
Link¨ ping University
o
SE-581 83 Link¨ ping, Sweden
o
E-mails: aamir.s.ahmed@gmail.com, Jacob.Wikner@liu.se
Abstract—This work describes the implementation of a 1.2- identical brightness levels across each horizontal line drawn
V programmable gain amplifier (PGA) for high-definition (HD) on the screen.
video digitizers in a 65-nm digital CMOS process.
The “pseudo” switched-capacitor (SC) PGA architecture
buffers the video signal, without switching, during the active
video. The SC circuitry is used for setup of DC operating point
during horizontal and vertical blanking periods. Additionally,
it compensates for the ’sync-tip’ of analog video signals to an
equal blanking level for increased dynamic range to the digitizer
following the PGA.
The operational transconductance amplifier (OTA) employed
as main amplifier in the PGA is a pseudo-differential, positive-
feedback input stage architecture with a common-mode feedfor-
ward (CMFF) technique. The common-mode feedback (CMFB)
is provided once two OTAs are cascaded.
Schematic-level simulation results show that the OTA main-
tains a −3-dB bandwidth of 550 MHz, while keeping the
distortion HD3 at –60 dB for a 30-MHz, 850 mVpp high definition
video signal. The 88 dB DC gain is distributed among four
OTA stages and the overall, combined PGA achieves a signal-
to-noise ratio of 63 dB. Due to only two stacked transistors, it
achieves high output swing of ±0.85 V, 1240 V/µs slew rate while
consuming 10.4 mW power.
Fig. 1. A video analog front-end (AFE) showing the interfacing circuits.
Index Terms—CMOS analog integrated circuits, switched
capacitor circuits, programmable gain amplifiers, feedforward
amplifiers, operational amplifiers In this work we propose a programmable gain amplifier
(PGA) for such high definition video analog front-ends. We
I. I NTRODUCTION have aimed the integration of AFE in a system-on-chip (SOC)
environment and have therefore explored a low-voltage imple-
The rapidly growing trends of home entertainment video in- mentation in a 65-nm digital CMOS process.
dustry has pushed the traditional video screens to deliver more Notice that the high-definition video and graphics stan-
detailed, high resolution and sharper pictures. With the advent dards have a high signal bandwidth. Signal frequencies up
of high definition progressive scanning (e.g. HDTV 1080p), to 30 MHz must be multiplexed, buffered and digitized with
video technology is bounded by stringent specifications, and high linearity maintained throughout the AFE. To prevent
any design lapse is more ”visible” than ever. The video analog other types of artifacts from appearing on the high-resolution
frontends have faced its direct impact, which coupled with picture screen, a bandwidth up to 20 times higher is required.
lower supplies and scaled sub-micron digital processes, make For the high-resolution graphics formats the bandwidth needs
the design more challenging. to be beyond 500 MHz. This type of bandwidth puts high
A typical modern video analog front-end (AFE) receiver requirements on the open-loop unity-gain bandwidth of the
chain is outlined in Fig. 1 (digital parts omitted). An AC PGA. These specifications are considerably more challenging
coupled video signal which is multiplexed and selected from compared to previously reported video PGAs such as [1].
a set of different input sources (there could be many video An example of an analog video signal waveform is shown
sources connected to the same TV set) is buffered. Inside the in Fig. 2. The active video region contains the vital picture
AC capacitor there is no connection to ground, i.e., no leakage. information, whereas the blanking intervals synchronize dur-
The signal is possibly amplified or attenuated by the PGA to ing the minimal black-time between successive frames and
adjust the levels to fit the digitizing ADC range. The signal horizontal lines. The blanking period typically contains a
leakage is prevented or restored by a clamp circuit, ensuring −40 IRE sync-tip, followed by a color burst (dependent on
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2. video formats) which provide amplitude, phase reference for
each color. Traditionally, the clamping occurs during the back-
porch duration.
Fig. 2. A typical analog video waveform. Fig. 3. The proposed video PGA including DC conditioning SC input.
In Section II we outline the PGA architecture and its
implementation for a video digitizing AFE to be used in SOCs. B. Gain Settings
In Section III the low-voltage OTA architecture is presented The gain settings are achieved by means of capacitor
and discussed. Simulation results are given in Section IV and ratios, and for the input video signals we have provided two
finally the paper is concluded in Section V. gain settings: 0.5 and 1. Capacitor Cin is then changed to
accomplish this programmable gain.
II. P ROPOSED V IDEO PGA C IRCUIT
It should be mentioned that some lower voltage swing video
The proposed video programmable gain amplifier (PGA) formats may require higher gain settings (2 times) to enable a
is realized as a fully-differential, ”pseudo” switched-capacitor more efficient utilization of the ADC. However, this increases
(SC) circuit that gets the multiplexed, clamped and band- the capacitive load on the PGA and the signal, thus decreasing
limited video signal from the first parts of the AFE. the system bandwidth. Such video formats, however, have
One has to consider a couple of points before outlining a bandwidth requirements much lower than 500 MHz too, and
video PGA using an SC technique, mainly: would not really suffer from the impact of lower bandwidth.
• The circuit must not switch during the active video The next section describes a four-stage, low-voltage pseudo-
duration of the analog video signal, to preserve a higher differential OTA architecture that is used in the PGA circuit.
signal linearity.
• In order to increase the signal dynamic range, the PGA
III. P SEUDO -D IFFERENTIAL OTA A RCHITECTURE
compensates for the sync-tip of analog video waveform, Various designs of low-voltage OTAs have been proposed in
presenting the ADC a sync-tip free signal. the literature, including for example [2]–[4]. We have explored
a pseudo-differential design, which eliminates the tail current
A. ”Pseudo” SC Circuit with Sync-Tip Compensation source in the input differential pair and becomes particularly
With the above considerations, we propose an SC architec- suited for low voltage design. One pseudo-differential OTA
ture where charge is transferred between the nodes during the with a CMFF strategy is presented in [5]–[7]. These designs
sync-tip duration only, which means the non-overlapping clock were originally implemented in a 0.5-μm CMOS process and
generator does not function beyond the sync-tip duration. In for higher supply voltage. We wanted to explore the design in
the absence of a sync-tip, i.e., during active video, the PGA a more modern SOC environment such as a 65-nm process.
acts like a capacitive buffer. However, porting of the originally proposed architecture to
Additionally, we exploit the fact, that most often the real a (relatively) much smaller dimension does have problems.
input video signal is single ended, and the second input of the These problems are foremost due to the low-gain devices
PGA is referenced from an on-chip, programmable digital-to- available among the core devices in an SOC process.
analog converter (DAC). We utilize this reference DAC voltage Thus the PGA in our work is realized using a modified OTA
to level-shift the sync-tip duration of video signal, effectively architecture, which has a positive feedback pseudo-differential
canceling the sync-tip, and obtaining a clean output signal. input stage for higher gain, but additionally for achieving the
The resulting SC architecture is shown in Fig. 3. Notice higher targeted video bandwidth, linearity, etc. The pseudo-
that the first two switches triggered by presence or absence differential OTA architecture with its inherent common-mode
of sync-tip, provide separate reference DC levels Vsync and feedforward also provides efficient common-mode feedback
VCM . Vsync is then the sync-tip voltage level (≈ −0.3 V (CMFB), when a similar OTA is cascaded! This saves us
or −40 IRE) and VCM is the input common-mode level. an additional CMFB block as proposed in [5] and shown in
This level is maintained in accordance with the input signal Fig. 4. The second stage OTA provides the first stage with
brightness. a common-mode feedback signal. Instead of using a separate

3. transconductance for common-mode detection as in [8], [9], The two most dominant poles found in the OTA stage are
the OTA utilizes the differential transconductance to detect the given by
input common-mode level too.
gm5 − (gds1 + gds2 + gds5 + gm2 )
ωp1 = ,
Cz
and
gds3 + gds4
ωp2 = ,
CL
where Cz is the parasitic capacitance at the output of the input
differential pair (also illustrated in Fig. 5) and CL is the load
capacitance at output node creating the most dominant pole.
Fig. 4. The cascaded OTA blocks to provide CMFB.
B. CMFB Detection
As mentioned above, the common-mode component is ex-
The positive-feedback OTA with its CMFF is shown tracted in the Vcm node of the OTA (see Fig. 5). In a multi-
in Fig. 5. The individual input stage currents are further stage OTA configuration, this Vcm voltage inside any OTA is
copied using a differential transconductance to detect the the sensed output common-mode level of the preceding OTA.
common-mode component in the OTA node Vcm . The detected Exploiting this property, one can provide CMFB as long as
common-mode current, (I1 + I2 )/2, is then subtracted at at least two OTAs are used in the chain (see Fig. 4). The
the output performing the feedforward cancellation. Due to first OTA adds an additional set of devices in parallel to the
similar differential-mode and common-mode signal paths the biasing PMOS of the output stage, which are controlled by the
bandwidths for both loops can be made fairly identical. fed back Vcm , and shown in Fig. 6 as VcmN ext . A common-
mode reference current is further mirrored in the output stage,
which then adjusts output DC point to its optimum level by
comparing the currents.
Fig. 5. The positive feedback pseudo-differential OTA with inherent Fig. 6. One half of the pseudo-differential architecture with CMFF and
common-mode feedforward. CMFB.
A. OTA Parameters C. Nonlinearity
To further describe the OTA design, some of the important Since the pseudo-differential input pairs remove the tail
design parameters are presented in this section. The DC gain current source, the amplifier will be more sensitive towards
ADC of the positive feedback input stage OTA is: mismatch variations. This implies that the second-order har-
gm1 gm4 monic distortion (HD2 ) will be larger than for a differential
ADC = , input pair with tail current source. Cross coupling between
(gm5 − (gm2 + gds1 + gds2 + gds5 ))(gds3 + gds4 )
gm1 gm4 differential signal and any common-mode interferer also con-
≈ , tributes to HD2 components. HD3 is contributed by short
(gm5 − gm2 )(gds3 + gds4 )
channel effects, as well as due to non-linear interaction of
where gmi is the transconductance of transistor Mi and gdsi differential OTA outputs and CMFB. A more detailed analysis
is the output conductance (or channel length modulation) of of sources of non-linearity in pseudo-differential designs is
transistor Mi . presented in [7].

4. Parameter [10] [11] [12] This work
D. Noise and SNR Process (nm) 90 350 90 65
Considering only transistor thermal noise, the input referred Supply (V) 1.2 1.8 2.5 1.2
2 DC gain (dB) 40 12 45 88*
noise power density, Pn = Vn−rms , of the positive feedback f3dB (MHz) 240 400 500 550
OTA architecture (omitting the common-mode noise contrib- Input Referred Noise 4.6 15 5.7 12.6
√
utors M6 , M7 , see Fig. 5) becomes: (nV/ Hz) @40 dB @0 dB @88 dB
THD −30 −40 - −60
16kT · BW E 2gm3 E + 2gm4 E + gm5 E HD3 (dB) @80 MHz @0.8Vpp @30 MHz
· 1+ + 2 ,
3gm1 gm2 gm1 gm1 gm4 Power (mW) 3.48 2.1 32.5 10.4
TABLE II
where BW is the equivalent noise bandwidth. E is a factor C OMPARISON OF RECENT PGA S (* OPEN - LOOP GAIN ).
given by E = (gm2 − gm5 )2 and once E ≈ 0, i.e., the
transconductance of the mirror transistors is approximately
equal to that of positive feedback transistors, the signal-to-
noise ratio (SNR) at the input becomes: V. C ONCLUSION
2
3gm1 HD3 Vef f (1 + θ Vef f ) (2 + θ Vef f ) We have described a programmable gain amplifier archi-
SNR ≈ 10 · log10 [ ]
2kT · BW tecture for high definition video standards that provides sync-
It can be noted that the positive feedback architecture clearly tip compensation using SC techniques. We maintained a low-
achieves a better SNR than the one derived originally in [7]. voltage implementation in a modern short channel process to
attain the challenging specifications of targeted video stan-
IV. S IMULATION R ESULTS dards. The novel pseudo-differential multi-stage OTA archi-
Table I compiles the simulation results for the PGA/OTA tecture with CMFB was enhanced to provide higher gain and
and in Table II the results are compared to other reported bandwidth, wider output swing and low distortion, to process
results. the video signals for best visual performance.
In Fig. 7 we show the simulated transient response for an R EFERENCES
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