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Accelerated development in Automotive E/E Systems using VisualSim Architect
- 1. Accelerated development in Automotive E/E Systems using VisualSim Architect
- 2. Logistics of the Webinar 2 All attendees will be placed on mute To ask a question, click on Cloud Chat sign and type the question. Folks are standing by to answer your questions. There will also be a time at the end for Q&A
- 3. Agenda Trends Key Automotive E/E systems technologies – Hardware, Networking and Software Introduction to system modeling – assembling Automotive E/E systems Examples and Use Cases Mirabilis Design and VisualSim Architect
- 4. Challenges in the Development of E/E Systems for Auto Require a single communication, tracking, exploration and testing mechanism from Requirements to post-sales diagnostics What-if study platform to scale from a small experiment to the complete vehicle architecture Link all studies with exploration and generation of tests Hardware, software and network teams must work of a single specification evaluation platform Trade-off must incorporate performance, power and functionality vs., safety, reliability, quality and cost
- 5. VisualSim Automotive E/E System Development Platform •VisualSim Architect can model the complete Automotive Electrical/Electronic system • Hardware • Software • Network •VisualSim models can evaluate • Performance • Power • Functionality •System can be tested for faults • Hardware failure • Software failure • RTOS failure • Power failure • Network failure
- 6. Key VisualSim Technologies Networking Protocols ◦ CAN, CAN/FD, FlexRay, AVB/TSN/TTE/GiE, AFDX, 5G/6G, Limited V2V Hardware and Software ◦ Gateways, switches, processor, schedulers, arbitrations, queues and Tx/Rx ◦ Task graph, software code execution, hardware programming integration Infrastructure and Integration ◦ Traffic generation (Distribution, CSV, random variation and trace), ARXML, Wireshark, Test instruments ◦ Cybersecurity, failure modes, error generation ◦ Distributed multi-core simulation All-in-One package for Network Analysis, Verification and Testing
- 7. Why Study Bandwidth Allocations & Timing Deadline? T3 Expected T3 Complete Consider three Packets- T1, T2 and T3 All tasks allocated to a single channel Each Task has equal processing time and priority (T1>T2>T3) Design Impacts of buffering, preemption, offset times and processing capacity Challenges must be studied globally, multiple attributes dependency is static and dynamic
- 8. Selecting the right Architecture Scheduling/Arbitration proportional share WFQ static dynamic fixed priority EDF TDMA FCFS Communication Templates Architecture # 1 Architecture # 2 Computation Templates DSP AI GPU DRAM CPU FPGA m E DSP TDMA Priority EDF WFQ RISC DSP LookUp Cipher AI DS P CPU GP U mE DD R static Which architecture is better suited for our application?
- 9. Architecture Exploration Methodology Product Concept, Optimized Architecture, Development and Support Handle 3 cameras, 4 Lidars & 5 Radars 95% cache hit-ratio Gateways to handle WiFi, BLE and TSN Power consumption Safety and security Product Requirements Output Optimized Architecture CPU_1 CPU_2 Cache RAM B U S Rough/Existing Architecture Semiconductor Systems and Software Assemble Models Conduct Trade-offs Architecture Optimization Functional Analysis VisualSim Environment Mirabilis Design Inc. 9 HW, SW and Network Development Documentation
- 10. AI Links Requirements with exploration Optimize Parameter to meet the requirements Requirements Database System Model Recommendations Diagnostics
- 11. System Model Experiments Different Gate Control Lists (GCL) for Time Aware Shaper (TAS) to meet timing deadlines Credit Based Shaper vs Strict Priority scheduling ◦ To meet bandwidth requirements for Audio Video Bridging (AVB) Class A and Class B frames. Scalability test ◦ More nodes, more traffic, more variations Performance with and without redundancy Experiments the software mapping sequences ◦ Sequential execution vs parallel execution vs cascaded execution
- 12. Common Evaluation Statistics Response times for safety critical tasks Throughput across Bus networks Packet drop rate across buffers, networks Memory usage CPU utilization Power consumption over a period of time – peak , avg power monitoring Battery discharge rate – with and without data encryption Credit analysis with frozen and non-frozen credit during GB (Guard Band) 11/10/2022 MIRABILIS DESIGN INC. 12
- 13. Use case examples Network Modelling ◦ Network side of the automotive E/E system ◦ Quality of Service settings, routing algorithms, topology etc. Software Modelling ◦ Software definition and mapping of tasks in automotive ◦ Task cascading, task graph definition, execution of software code Hardware Modelling ◦ Hardware architecture of the automotive E/E system ◦ ECU design, resource management etc. Failure Analysis ◦ Injecting faults at various levels within automotive E/E system ◦ Hardware, Software, Power, RTOS and Networking Content
- 14. Network Modelling – Use Cases
- 15. Time Sensitive Networking (TSN) Standard case study – CBS vs Strict Priority •Agenda – Evaluate the performance gains – throughput, packet spacing , when using Credit Based Shaper enabled Switch vs a Strict Priority scheduler enabled switch. •Traffic – Class B traffic sent via Port A at an average rate of 90 Mbps and Best Effort (Priority 7) frames sent via port B at an average rate of 60 Mbps. Both AVB and BE frames are to be sent to the same destination port, port C. •Credit based shaper – Based on the sendslope and idleslope settings, bandwidth allocated for class A and class B can be moderated. AVB frames given higher priority than BE frames. • Idleslope = (Reservation_value * 1000000) / 8 • Sendslope = (Port transmission rate – Reservation_value)* 1000000) / 8 •Strict Priority scheduler – Scheduler gives resources to the higher priority frames first. Typically, AVB frame Class A mapped to Priority 5 and Class B mapped to Priority 4.
- 17. USE CASE - 1 CREDIT BASED SHAPER – RESERVATION_VALUE = 55.0 Mbps
- 18. Parameter settings Calculations - • Reservation_value = 55 Mbps • Idleslope = (Reservation_value * 1000000) / 8 = 6.875E6 bps = 6.875 Mbps • Sendslope = (Port transmission rate – Reservation_value)* 1000000) / 8 = 5.625E6 bps = 5.625 Mbps
- 19. Results • Egress throughput shows that the AVB class could only use a maximum of 55 Mbps. The remaining 45 Mbps was used by BE frames • The Egress packet spacing looks considerably better without the abrupt spikes seen in the Ingress spacing.
- 20. USE CASE - 2 STRICT PRIORITY SCHEDULER – NO CBS
- 22. Results • Here, since BE frame has higher priority (7) than the AVB class B (4), BE frames are sent ahead of AVB frames and thus more bandwidth is consumed by the BE frames, shown by the Egress throughput plot. • Better packet spacing is seen for BE frames.
- 23. Complex Multi-Layer Network Model Multi-agent traffic, Multi-protocol network studies
- 24. Exploring Protocols Meet QoS Evaluate algorithms, QoS strategies and detect bottlenecks
- 25. Software Modelling – Use Cases
- 26. Evaluate Software Partitioning Model the entire Vehicle for a realistic analysis Hardware architecture / network topology Software sequence Sensors connected to the TSN Switches send data periodically to the processing nodes/units distributed across the network. The software sequences are mapped to the hardware. Here we have 4 software functions defined: Function 2 and 3 can start when Function 1 completes and for Function 4 to start, both Function 2 and 3 must complete.
- 27. Metrics to Evaluate Quality
- 28. Hardware Modelling – Use Cases
- 29. Sub-System or System Evaluation Brake ECU
- 30. Power, Heat, Functional and Timing
- 31. Input Data to the System model Sensor Data file Map Tasks to Processor Cores Task Mapping Table
- 32. Stats Generated Task Stats TSN Switch stats
- 33. Failure Analysis – For improved safety and reliability
- 34. Failure Analysis in: Hardware One of the processor core dies. Tasks get remapped to active cores Reduced buffer size due to memory loss Data error due to Electro magnetic Interference Sudden occurrence of alarms which leads to more core activity Software Deadlock and Livelock Resource starvation RTOS App execution within a slot going over to the next slot and not meeting the slot schedule Power Thermal shocks and lifecycle loss Processor core shutdown due to not enough power Network Fault Injector Brute Force attack
- 35. Hardware with failure without failure • Core failure – Core_1 is damaged. As a result, all core_1 tasks are mapped to other active cores (refer Timing Diagram) • EM Interference – Causes data corruption (refer logfile) • Memory loss – Total available space to which data can be written is reduced (refer logfile) • Burst Traffic – Sudden activation of alarm causes increased workload on processor cores (refer latency plot)
- 36. Software Failure The model represents the read and write problem and how to resolve it. Initially, data is read, then data is updated the result will be analyzed by identifying the read data = write data and if it is not, another request will be sent to fetch updated value. So this model represents the failure, when the algorithm result change due to the changes in memory value. Incorrect Data packets Correct Data packets Read & Write Problem
- 38. Detecting and handling Deadlock – Task Graphs No deadlock Deadlock due to credits not being released for flow 0 Flow 0 not being executed anymore
- 39. Detecting and handling Livelock Livelock detected. Instructions are being executed in loop at an unexpected label From the per label stats, we can see a set of instructions being executed at very high occurrence and the latency keep going up Without livelock With livelock
- 40. RTOS Failure Disabled slot due to greater execution time of the task This model represents multiple tasks running at different slots in a processor core. If the time it took to complete execution of an application of a particular slot exceeds the threshold, then that slot will be disabled and restarted after the restart time. The latency for all the tasks that are running for each of the slot is calculated. Disabled slot information will be printed on the console window.
- 41. Core shutdown due to low power availability Without power drop With power drop Latency at higher value
- 42. Network Fault Injector Different types of failure
- 43. Results No Faults injected Message Loss injected Incorrect Addressing
- 44. Glimpses into the future
- 45. TC10 Integrated Software sw1 sw2 sw3 Node1 Node2 Node3 Node4 Node5 • Wake up event on “Node5”; Need to talk to “Node2” • Wake up information has to go through links A, B, C and D • Link C is already active! A B C D - Active ECU - ECU sleeping - Active port - Port down Active link Link down Software Software Abstraction Hardware • Multiple services per hardware • The software defines the hardware
- 47. About Mirabilis Design Engineering Solutions focused on innovation in electronics Based in Silicon Valley, USA Development and support centers in US, India, Japan, China and Czech 60 large corporations, research centers and 73 universities as customers Enabled 250 products in semiconductors, automotive, defense and space VisualSim Architect is the system simulation and IP for hardware, software and networking
- 48. Mirabilis Design – Milestones VisualSim Aerospace Simulator of the Year Hardware Modeling 2003 Company Incorporated 2005 Modeling Services 1st Customer 2008 Stochastic Modeling Innovation Award 2010 Integration API 10th customer 2011 Network Modeling University Program 2013 2015 2018 Best ESL at DAC 2nd at Arm TechCon 2019 VisualSim Automotive Europe operations 2020 Failure Analysis Created Asia Team 2021 Best Embedded Systems Presentation Award – DAC 2021 SysML API Requirements 2018 New VisualSim 2022 Best in Show Embedded World 2023 Communication System Designer 2022 System Verilog and UPF/CPF Link
- 49. VisualSim Architect Cloud and Desktop Multi-simulation engine- Digital, Untimed & Continuous Library of Systems, Networks, Semi, FPGA & Software Generate statistics, documentation & traces Algorithms Protocol AI Insight Performance Power Functional Stochastic Scripting Sim API Performance Latency, Throughput, Buffer occupancy Power Instant, Average, Cumulative, Heat, Temperature Battery and power generation sizing Functionality Correctness, efficiency and Quality-of-Service Failure Analysis and Functional Safety Generate errors and test for compliance Software Evaluation Test quality of C++ and impact on system performance System-level Modeling and Simulation Software that integrates requirements, exploration & verification
- 50. Over 500 Systems-Level IP Components Comprehensive implementation-accurate Library Traffic • Distribution • Sequence • Trace file • Instruction profile Power • State power table • Power management • Energy harvesters • Battery • RegEx operators SoC Buses • AMBA and Corelink • AHB, APB, AXI, ACE, CHI, CMN600 • Network-on-Chip • TileLink System Bus • PCI / PCI- X / PCIe • Rapid IO • AFDX • OpenVPX • VME • SPI 3.0 • 1553B ARM • M-, R-, 7TDMI • A8, A53, A55, A72, A76, A77, Neoverse Custom Creator • Script language • 600 RegEx fn • Task graph • Tracer • C/C++/Java • Python Stochastic • FIFO/LIFO Queue • Time Queue • Quantity Queue • System Resource • Schedulers • Cyber Security Memory • Memory Controller • DDR DRAM 2,3,4, 5 • LPDDR 2, 3, 4 • HBM, HMC • SDR, QDR, RDRAM Networking • Ethernet & GiE • Audio-Video Bridging • 802.11 and Bluetooth • 5G • Spacewire • CAN-FD • TTEthernet • FlexRay • TSN & IEEE802.1Q • ARINC 664/AFDX Interfaces • Virtual Channel • DMA • Crossbar • Serial Switch • Bridge Algorithms • Signal Processing • Analog • Antenna RTOS • Template • ARINC 653 • AUTOSAR Storage • Flash & NVMe • Storage Array • Disk and SATA • Fibre Channel • FireWire Software • GEM5 • Software code integration • Instruction trace • Statistical software model • Task graph RTL-Like • Clock, Wire-Delay • Registers, Latches • Flip-flop • ALU and FSM • Mux, DeMux • Lookup table Processors • GPU, DSP, mP and mC • RISC-V • SiFive u74 • Nvidia- Drive-PX • PowerPC • X86- Intel and AMD • DSP- TI and ADI • MIPS, Tensilica, SH Reports • Timing and Buffer • Throughput/Util • Ave/peak power • Statistics FPGA • Xilinx- Zynq, Virtex, Kintex • Intel-Stratix, Arria • Microsemi- Smartfusion • Programmable logic template • Interface traffic generator
- 51. Using Code-based Design Methodology Project Schedule Model Creation (6) Implementation (18) Analysis (1.5) Communication and Refinement (6) Implementation (15) Using Model-Based Design Methodology Note: All times in months Communication and Refinement (4) Analysis (2.5) Model Creation (1) System Modelling Benefits Average gain for 24 month project is 25%-30% Highest Quality Product Accelerate Model development Average increase in revenue per project = $??M
- 52. Accelerated development in Automotive E/E Systems using VisualSim Architect