This document summarizes research on 3D network-on-chip architectures. It begins by introducing the benefits of 3D integrated circuits for reducing wire lengths and improving performance. It then surveys several existing 3D NoC architectures:
1) Symmetric NoC which treats intra-layer and inter-layer hops identically, incurring high overhead.
2) NoC-Bus Hybrid which uses a bus for single-hop vertical links to reduce hops.
3) Ciliated 3D Mesh which restricts switches to layers and adds cores per switch, lowering bandwidth.
4) True 3D NoC Router which embeds vertical links directly in crossbars for seamless routing.
The
This summary provides the key details about the document in 3 sentences:
The document describes the implementation of a 1.2-V 500-MHz programmable gain amplifier (PGA) for high-definition video digitizers in a 65-nm CMOS process. The PGA uses a pseudo switched-capacitor architecture that buffers the video signal without switching during active video and uses the switched-capacitor circuitry for setup of the DC operating point during blanking periods. Simulation results show the PGA maintains -3dB bandwidth of 550 MHz and distortion of -60dB for a 30-MHz 850mVpp HD video signal while consuming 10.4mW power.
This document summarizes a research paper that describes how to design a simple dataflow processor using the functional hardware description language CλaSH. The key points are:
1) CλaSH compiles Haskell code into synthesizable VHDL, allowing hardware to be specified at a high level of abstraction close to mathematical descriptions.
2) The paper presents the design of a dataflow processor as an example, implemented as a static dataflow machine with an explicit token store for efficient token storage.
3) The processor design consists of a router, matcher, and ALU modules connected by buffers. The matcher implements the token matching process that triggers operations in dataflow fashion.
This document proposes a calibration technique for sigma-delta analog-to-digital converters (ΣΔADCs) that uses histogram test methods. The technique can calibrate errors in the flash subADC as well as other components, including the DAC and accumulator. It works by applying an analog signal with a known probability distribution to the converter input and recording the number of occurrences of digital output codes. Differences between the actual and expected output distributions are used to estimate linearity, gain, and offset errors, which can then be corrected. Simulation results show the technique improves the effective number of bits from 6.6 to 11.3 while correcting for large introduced errors, demonstrating its robustness.
The document describes a modified Dickson charge pump design that reduces power consumption during input clock transitions. A PMOS transistor is added in series with each capacitor stage to increase the time constant, slowing the charge transfer. This reduces power from 340.5uW to 28.85uW at no load for the Dickson versus modified design. Output voltages are similar but slightly lower for the modified design. At 10MOhm and 40MOhm loads, power savings during transitions are also realized compared to the standard Dickson design while maintaining comparable output voltages. In conclusion, the modified design successfully reduces transition power consumption without significantly impacting output voltage.
This document describes a novel transimpedance amplifier with variable gain. It proposes a new topology using only three active devices and no passive components. Simulations show it achieves comparable noise, bandwidth, and input impedance as a conventional design using 30uW power. Its transimpedance gain can be varied from 68dB to 78dB by adjusting a control voltage, allowing for a 10dB range of programmability. The proposed design occupies less layout space and is well-suited for applications requiring many sensors.
1. The document presents a simulation of a low power analog channel decoder for error correction implemented in 65nm CMOS technology.
2. The decoder uses analog circuitry operating in the sub-threshold region to perform decoding, allowing for ultra-low power operation below 40uW for throughput up to 2.5Mbps.
3. The decoder architecture includes an analog decoding core that implements the sum-product algorithm, digital interfaces for input and output, and a digital controller to manage timing.
The document describes an improved interconnection network called Hybrid-2 for a Coarse Grain Reconfigurable Architecture called Dynamically Reprogrammable Resource Array (DRRA). Hybrid-2 allows for partial and dynamic runtime reconfiguration with fewer configuration bits than previous networks like Hybrid-1, multiplexers, networks-on-chip, and crossbars. Evaluation shows Hybrid-2 requires less area and configuration bits while providing faster configuration times compared to previous approaches.
This document summarizes research on 3D network-on-chip architectures. It begins by introducing the benefits of 3D integrated circuits for reducing wire lengths and improving performance. It then surveys several existing 3D NoC architectures:
1) Symmetric NoC which treats intra-layer and inter-layer hops identically, incurring high overhead.
2) NoC-Bus Hybrid which uses a bus for single-hop vertical links to reduce hops.
3) Ciliated 3D Mesh which restricts switches to layers and adds cores per switch, lowering bandwidth.
4) True 3D NoC Router which embeds vertical links directly in crossbars for seamless routing.
The
This summary provides the key details about the document in 3 sentences:
The document describes the implementation of a 1.2-V 500-MHz programmable gain amplifier (PGA) for high-definition video digitizers in a 65-nm CMOS process. The PGA uses a pseudo switched-capacitor architecture that buffers the video signal without switching during active video and uses the switched-capacitor circuitry for setup of the DC operating point during blanking periods. Simulation results show the PGA maintains -3dB bandwidth of 550 MHz and distortion of -60dB for a 30-MHz 850mVpp HD video signal while consuming 10.4mW power.
This document summarizes a research paper that describes how to design a simple dataflow processor using the functional hardware description language CλaSH. The key points are:
1) CλaSH compiles Haskell code into synthesizable VHDL, allowing hardware to be specified at a high level of abstraction close to mathematical descriptions.
2) The paper presents the design of a dataflow processor as an example, implemented as a static dataflow machine with an explicit token store for efficient token storage.
3) The processor design consists of a router, matcher, and ALU modules connected by buffers. The matcher implements the token matching process that triggers operations in dataflow fashion.
This document proposes a calibration technique for sigma-delta analog-to-digital converters (ΣΔADCs) that uses histogram test methods. The technique can calibrate errors in the flash subADC as well as other components, including the DAC and accumulator. It works by applying an analog signal with a known probability distribution to the converter input and recording the number of occurrences of digital output codes. Differences between the actual and expected output distributions are used to estimate linearity, gain, and offset errors, which can then be corrected. Simulation results show the technique improves the effective number of bits from 6.6 to 11.3 while correcting for large introduced errors, demonstrating its robustness.
The document describes a modified Dickson charge pump design that reduces power consumption during input clock transitions. A PMOS transistor is added in series with each capacitor stage to increase the time constant, slowing the charge transfer. This reduces power from 340.5uW to 28.85uW at no load for the Dickson versus modified design. Output voltages are similar but slightly lower for the modified design. At 10MOhm and 40MOhm loads, power savings during transitions are also realized compared to the standard Dickson design while maintaining comparable output voltages. In conclusion, the modified design successfully reduces transition power consumption without significantly impacting output voltage.
This document describes a novel transimpedance amplifier with variable gain. It proposes a new topology using only three active devices and no passive components. Simulations show it achieves comparable noise, bandwidth, and input impedance as a conventional design using 30uW power. Its transimpedance gain can be varied from 68dB to 78dB by adjusting a control voltage, allowing for a 10dB range of programmability. The proposed design occupies less layout space and is well-suited for applications requiring many sensors.
1. The document presents a simulation of a low power analog channel decoder for error correction implemented in 65nm CMOS technology.
2. The decoder uses analog circuitry operating in the sub-threshold region to perform decoding, allowing for ultra-low power operation below 40uW for throughput up to 2.5Mbps.
3. The decoder architecture includes an analog decoding core that implements the sum-product algorithm, digital interfaces for input and output, and a digital controller to manage timing.
The document describes an improved interconnection network called Hybrid-2 for a Coarse Grain Reconfigurable Architecture called Dynamically Reprogrammable Resource Array (DRRA). Hybrid-2 allows for partial and dynamic runtime reconfiguration with fewer configuration bits than previous networks like Hybrid-1, multiplexers, networks-on-chip, and crossbars. Evaluation shows Hybrid-2 requires less area and configuration bits while providing faster configuration times compared to previous approaches.
Vesyla is a high-level synthesis framework that maps DSP algorithms onto a coarse-grain reconfigurable architecture. It takes untimed C code as input and uses pragmas to guide the mapping and generation of configuration files for the architecture. The pragmas identify parallelism and allocate and bind operations and operands to resources. This allows the user to explore different architectural implementations from serial to fully parallel. Vesyla analyzes dependencies, schedules operations, and synchronizes parallel threads to generate the configuration files.
This document analyzes the energy dissipation of digital half band filters operated in the sub-threshold region with throughput constraints. It explores various architectures of a 12-bit half band filter including the basic implementation and unfolded structures. Simulation results show that the unfolded by 2 architecture dissipates 22% less energy per sample compared to the original filter, making it the most energy efficient. The unfolded by 4 architecture best meets throughput requirements of 120K-1M samples/sec, dissipating less energy than other implementations in this speed range.
This document discusses the design of a CMOS sampling switch for ultra-low power analog-to-digital converters (ADCs) used in biomedical applications. It analyzes general switch design constraints such as thermal noise, sampling time jitter, switch-induced error, tracking bandwidth, and voltage droop. Based on the analyses, a leakage-reduced CMOS sampling switch is designed for a 10-bit 1-kS/s successive approximation ADC using a 130nm CMOS process. Post-layout simulation shows the proposed switch offers an effective number of bits of 9.5 while consuming only 64 nW of power, meeting the ADC specification.
The document describes a distributed memory architecture for a coarse-grain reconfigurable architecture (CGRA) with network-on-chip (NoC) capabilities. The key aspects of the architecture are:
1) It uses a distributed memory approach with memory banks (mBanks) connected via a circuit-switched NoC to enable private and parallel execution environments (PREX).
2) The memory is partitionable and partitions can be reconfigured at runtime to modify the memory to computation ratio.
3) Controllers synchronize data streaming from mBanks to computation elements to improve performance and energy efficiency.
The document proposes the Layered Spiral Algorithm (LSA) for memory-aware application mapping and scheduling onto Network-on-Chip (NoC) architectures. LSA extends the existing spiral mapping algorithm to consider memory constraints and task scheduling. It models applications as Memory-Aware Communication Task Graphs (MACTG) and platforms as Platform Architecture Graphs (PAG). LSA aims to minimize energy consumption during mapping and scheduling while maintaining high parallelism. It compares results to optimal solutions from an Mixed Integer Linear Programming (MILP) formulation to evaluate performance.
The document presents a new NoC Interface (MSIQ) that improves performance over the previous MSI by reducing software overhead from interrupt processing. The MSIQ uses queue mechanisms to batch multiple interrupt requests and allow the interrupt service routine to process requests concurrently with hardware message sending and receiving. Performance analysis shows the MSIQ achieves better performance than the MSI with only small additional hardware costs.
This paper analyzes the effects of different Network-on-Chip (NoC) modeling styles in SystemC on simulation speed compared to a reference VHDL model. Two approximately timed (AT) and loosely timed (LT) transaction level (TL) models achieved 13-40x and 20-30x speedups respectively over the VHDL model with less than 10% error. The AT model offered a notable speedup with modest error and is recommended over the LT model which did not provide significant additional speedup despite larger estimation errors, especially under higher loads. Increasing transfer size and raising the abstraction level to transaction-level modeling were found to be effective methods to significantly improve simulation performance for evaluating NoC designs.
This document proposes a framework for modeling source traffic in a Network on Chip (NoC) that originates from a single source but is destined for multiple destinations, known as multicasting. It presents a model to characterize such traffic as a single stream at the source based on the probabilistic demultiplexing of that stream into multiple streams. The model shows that the burst parameters of the demultiplexed streams are related to those of the original stream. The model is implemented in an NoC simulator and experimental results validate that the demultiplexed streams remain bursty even as their burst parameters change according to the model.
This document proposes two genetic algorithm based methodologies called Minimum Spanning Tree First (MSTF) and Shortest Paths First (SPF) for designing customized and energy optimized irregular Network-on-Chip (NoC) topologies tailored to an application's communication characteristics. The MSTF methodology first constructs a minimum spanning tree and then extends the topology by adding shortest energy paths, while SPF first finds the shortest energy paths and then constructs the minimum spanning tree. Experimental results on random benchmarks show the SPF methodology reduces average dynamic communication energy by 18.5% on average compared to MSTF. SPF also achieves lower latency and similar throughput. Comparisons with regular 2D mesh NoCs and an intelligent mapping
This document reviews Network-on-Chip (NoC) architectures that prioritize selected data streams to reduce communication latency. It categorizes the architectures based on the effect of prioritization (per end-to-end connection, per router, or per path segment) and discusses their pros and cons. Architectures that prioritize at the core-to-core level provide the highest latency reduction by bypassing the NoC, while those prioritizing per router or path segment require redetermining priority at each hop.
The document proposes a hybrid network-on-chip (NoC) architecture that combines spatial division multiplexing (SDM)-based circuit switching and packet switching. The SDM-based circuit-switched sub-network handles streaming traffic, using SDM to increase path diversity and improve throughput. The packet-switched sub-network handles best-effort traffic and configures the circuit-switched sub-network. The hybrid router architecture was implemented in FPGA and ASIC, showing it can build a practical hybrid NoC while providing quality of service for streaming traffic without complex resource sharing.
This document proposes a new method called SfW (skewed-load for wrapper) for generating delay fault tests that can be applied through a simple boundary scan chain. The SfW method generates test vectors for transition faults in a way that consecutive vector pairs are generated by one or more bit shifts, reducing the test application time compared to random vectors. Experimental results on combinational and sequential circuits showed the SfW method provides a significant reduction in test vector application time compared to previous methods.
This document proposes a multi-application multi-step mapping method for mapping multiple applications simultaneously onto a many-core Network-on-Chip (NoC). The method consists of two steps: 1) an application mapping step that finds a region on the NoC for each application using maximal empty rectangle techniques, and 2) a task mapping step that maps the tasks of each application within its region to minimize communication latency and energy consumption. The method aims to optimize the layout of applications and tasks to reduce network latency and energy usage for multi-application mapping on many-core NoCs.
This paper presents a second-order delta-sigma modulator designed for pressure sensor applications. The modulator utilizes correlated double sampling in the first integrator to reduce flicker noise. It was implemented in a 0.35-μm CMOS process and consumes 14μA of current. Measurements showed a signal-to-noise ratio of 86dB at a 14-bit resolution level when using an input sampling rate of 1/4 and sampling capacitors of 50pF. The modulator provides a flexible design that allows tuning the sampling frequency and capacitor size to tradeoff between power consumption and performance.
The document describes an analog baseband chain for a Synthetic Aperture Radar (SAR) receiver implemented in a 130nm CMOS technology. The baseband chain consists of a three-stage Variable Gain Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF), and an Output Buffer (OBUF). The VGA provides a tunable gain range of 25-34dB. The LPF has a programmable bandwidth of 120-190MHz and provides an additional 8dB of gain. Together, the baseband chain achieves 4nV/√Hz of input-referred noise density and -42dBV of in-band IIP3. The chain occupies
This document discusses a proposed architecture for a higher Nyquist-range digital-to-analog converter (DAC) that employs sinusoidal interpolation.
[1] Conventional DACs operate within the Nyquist range, but the proposed architecture aims to utilize higher Nyquist ranges by approximating an oscillating signal from an RF DAC concept using sinusoidal interpolation in the time domain.
[2] The proposed architecture quantizes both the input signal and pulse amplitude modulation waveform and combines them digitally, replacing analog oscillatory circuits with a digital data stream. This reduces analog complexity compared to existing techniques.
[3] Simulation results and theoretical analysis are presented to support that the proposed architecture can provide similar performance
The document describes an 8-bit pipelined analog-to-digital converter (ADC) with a selectable resolution of 5-8 bits. The ADC was fabricated in a 0.13-micron CMOS process and achieves an effective number of bits of 6.10 in 8-bit mode with a 162 MHz input signal. Key aspects of the ADC include double sampling to relax amplifier settling times, redundant sign digit correction to compensate comparator offsets, and a two-stage op-amp design to provide sufficient gain and signal headroom given the low 1.2V supply voltage. Measured performance meets the requirements for medium resolution and sampling rate ADCs in modern synthetic aperture radar systems.
This paper presents an improved hardware acceleration scheme for Java method calls in the REALJava coprocessor. The strategy is implemented in an FPGA prototype and allows for measuring real performance increases. It validates the coprocessor concept for accelerating Java bytecode execution in embedded systems with limited CPU performance and memory availability. The coprocessor architecture is highly modular, separating communication from the execution core to improve reusability and allow for system scalability.
The document summarizes developments made to a System on Chip (SoC) to support higher order QAM modulation for wireless systems operating at 38 GHz. Key developments include:
1) Increasing the resolution of analog-to-digital converters and digital-to-analog converters from 8-10 bits to 10-12 bits to support 64QAM modulation.
2) Design improvements to suppress internal clock jitter to less than ±50 picoseconds to enable effective operation with higher resolution converters.
3) Development of a prototype SoC that enables 64QAM modulation, with an architecture that supports up to 256QAM, and achieves an effective throughput of 1 Gbps.
1) Current-steering DACs often have non-linearity due to signal-dependent output impedance, which causes 2nd-order distortion.
2) When used for digital IF generation rather than direct up-conversion, the DAC output contains tones at the desired IF frequency and its harmonics/images.
3) The dominant source of distortion is mixing between the output voltage and digital input signal, generating intermodulation products. Shorting unwanted tones at the DAC output could improve linearity.
The document describes a high-resolution time-to-digital converter (TDC) implemented in a 90nm CMOS process. It uses two gated ring oscillators (GROs) as delay lines in a Vernier structure to achieve both a high time resolution and first-order noise shaping. The TDC achieves less than 10ps coarse resolution, consumes 3.6mA from a 1.2V supply, and occupies an active area of 0.18mm by 0.15mm. Simulation results show the quantization noise is pushed to high frequencies, improving the in-band noise performance for applications like all-digital phase-locked loops.
This document describes novel multi-threshold voltage level converters that minimize power consumption without compromising speed. Conventional feedback-based level converters rely on feedback circuits that cause slow response times and short circuit currents. The novel converters proposed use multiple transistor threshold voltages to directly drive high voltage gates from low voltage signals without static currents. When used in an integrated circuit, the multi-threshold converters decrease power by 47% and optimize delay by 50% compared to feedback converters in a 0.18-μm technology.
Vesyla is a high-level synthesis framework that maps DSP algorithms onto a coarse-grain reconfigurable architecture. It takes untimed C code as input and uses pragmas to guide the mapping and generation of configuration files for the architecture. The pragmas identify parallelism and allocate and bind operations and operands to resources. This allows the user to explore different architectural implementations from serial to fully parallel. Vesyla analyzes dependencies, schedules operations, and synchronizes parallel threads to generate the configuration files.
This document analyzes the energy dissipation of digital half band filters operated in the sub-threshold region with throughput constraints. It explores various architectures of a 12-bit half band filter including the basic implementation and unfolded structures. Simulation results show that the unfolded by 2 architecture dissipates 22% less energy per sample compared to the original filter, making it the most energy efficient. The unfolded by 4 architecture best meets throughput requirements of 120K-1M samples/sec, dissipating less energy than other implementations in this speed range.
This document discusses the design of a CMOS sampling switch for ultra-low power analog-to-digital converters (ADCs) used in biomedical applications. It analyzes general switch design constraints such as thermal noise, sampling time jitter, switch-induced error, tracking bandwidth, and voltage droop. Based on the analyses, a leakage-reduced CMOS sampling switch is designed for a 10-bit 1-kS/s successive approximation ADC using a 130nm CMOS process. Post-layout simulation shows the proposed switch offers an effective number of bits of 9.5 while consuming only 64 nW of power, meeting the ADC specification.
The document describes a distributed memory architecture for a coarse-grain reconfigurable architecture (CGRA) with network-on-chip (NoC) capabilities. The key aspects of the architecture are:
1) It uses a distributed memory approach with memory banks (mBanks) connected via a circuit-switched NoC to enable private and parallel execution environments (PREX).
2) The memory is partitionable and partitions can be reconfigured at runtime to modify the memory to computation ratio.
3) Controllers synchronize data streaming from mBanks to computation elements to improve performance and energy efficiency.
The document proposes the Layered Spiral Algorithm (LSA) for memory-aware application mapping and scheduling onto Network-on-Chip (NoC) architectures. LSA extends the existing spiral mapping algorithm to consider memory constraints and task scheduling. It models applications as Memory-Aware Communication Task Graphs (MACTG) and platforms as Platform Architecture Graphs (PAG). LSA aims to minimize energy consumption during mapping and scheduling while maintaining high parallelism. It compares results to optimal solutions from an Mixed Integer Linear Programming (MILP) formulation to evaluate performance.
The document presents a new NoC Interface (MSIQ) that improves performance over the previous MSI by reducing software overhead from interrupt processing. The MSIQ uses queue mechanisms to batch multiple interrupt requests and allow the interrupt service routine to process requests concurrently with hardware message sending and receiving. Performance analysis shows the MSIQ achieves better performance than the MSI with only small additional hardware costs.
This paper analyzes the effects of different Network-on-Chip (NoC) modeling styles in SystemC on simulation speed compared to a reference VHDL model. Two approximately timed (AT) and loosely timed (LT) transaction level (TL) models achieved 13-40x and 20-30x speedups respectively over the VHDL model with less than 10% error. The AT model offered a notable speedup with modest error and is recommended over the LT model which did not provide significant additional speedup despite larger estimation errors, especially under higher loads. Increasing transfer size and raising the abstraction level to transaction-level modeling were found to be effective methods to significantly improve simulation performance for evaluating NoC designs.
This document proposes a framework for modeling source traffic in a Network on Chip (NoC) that originates from a single source but is destined for multiple destinations, known as multicasting. It presents a model to characterize such traffic as a single stream at the source based on the probabilistic demultiplexing of that stream into multiple streams. The model shows that the burst parameters of the demultiplexed streams are related to those of the original stream. The model is implemented in an NoC simulator and experimental results validate that the demultiplexed streams remain bursty even as their burst parameters change according to the model.
This document proposes two genetic algorithm based methodologies called Minimum Spanning Tree First (MSTF) and Shortest Paths First (SPF) for designing customized and energy optimized irregular Network-on-Chip (NoC) topologies tailored to an application's communication characteristics. The MSTF methodology first constructs a minimum spanning tree and then extends the topology by adding shortest energy paths, while SPF first finds the shortest energy paths and then constructs the minimum spanning tree. Experimental results on random benchmarks show the SPF methodology reduces average dynamic communication energy by 18.5% on average compared to MSTF. SPF also achieves lower latency and similar throughput. Comparisons with regular 2D mesh NoCs and an intelligent mapping
This document reviews Network-on-Chip (NoC) architectures that prioritize selected data streams to reduce communication latency. It categorizes the architectures based on the effect of prioritization (per end-to-end connection, per router, or per path segment) and discusses their pros and cons. Architectures that prioritize at the core-to-core level provide the highest latency reduction by bypassing the NoC, while those prioritizing per router or path segment require redetermining priority at each hop.
The document proposes a hybrid network-on-chip (NoC) architecture that combines spatial division multiplexing (SDM)-based circuit switching and packet switching. The SDM-based circuit-switched sub-network handles streaming traffic, using SDM to increase path diversity and improve throughput. The packet-switched sub-network handles best-effort traffic and configures the circuit-switched sub-network. The hybrid router architecture was implemented in FPGA and ASIC, showing it can build a practical hybrid NoC while providing quality of service for streaming traffic without complex resource sharing.
This document proposes a new method called SfW (skewed-load for wrapper) for generating delay fault tests that can be applied through a simple boundary scan chain. The SfW method generates test vectors for transition faults in a way that consecutive vector pairs are generated by one or more bit shifts, reducing the test application time compared to random vectors. Experimental results on combinational and sequential circuits showed the SfW method provides a significant reduction in test vector application time compared to previous methods.
This document proposes a multi-application multi-step mapping method for mapping multiple applications simultaneously onto a many-core Network-on-Chip (NoC). The method consists of two steps: 1) an application mapping step that finds a region on the NoC for each application using maximal empty rectangle techniques, and 2) a task mapping step that maps the tasks of each application within its region to minimize communication latency and energy consumption. The method aims to optimize the layout of applications and tasks to reduce network latency and energy usage for multi-application mapping on many-core NoCs.
This paper presents a second-order delta-sigma modulator designed for pressure sensor applications. The modulator utilizes correlated double sampling in the first integrator to reduce flicker noise. It was implemented in a 0.35-μm CMOS process and consumes 14μA of current. Measurements showed a signal-to-noise ratio of 86dB at a 14-bit resolution level when using an input sampling rate of 1/4 and sampling capacitors of 50pF. The modulator provides a flexible design that allows tuning the sampling frequency and capacitor size to tradeoff between power consumption and performance.
The document describes an analog baseband chain for a Synthetic Aperture Radar (SAR) receiver implemented in a 130nm CMOS technology. The baseband chain consists of a three-stage Variable Gain Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF), and an Output Buffer (OBUF). The VGA provides a tunable gain range of 25-34dB. The LPF has a programmable bandwidth of 120-190MHz and provides an additional 8dB of gain. Together, the baseband chain achieves 4nV/√Hz of input-referred noise density and -42dBV of in-band IIP3. The chain occupies
This document discusses a proposed architecture for a higher Nyquist-range digital-to-analog converter (DAC) that employs sinusoidal interpolation.
[1] Conventional DACs operate within the Nyquist range, but the proposed architecture aims to utilize higher Nyquist ranges by approximating an oscillating signal from an RF DAC concept using sinusoidal interpolation in the time domain.
[2] The proposed architecture quantizes both the input signal and pulse amplitude modulation waveform and combines them digitally, replacing analog oscillatory circuits with a digital data stream. This reduces analog complexity compared to existing techniques.
[3] Simulation results and theoretical analysis are presented to support that the proposed architecture can provide similar performance
The document describes an 8-bit pipelined analog-to-digital converter (ADC) with a selectable resolution of 5-8 bits. The ADC was fabricated in a 0.13-micron CMOS process and achieves an effective number of bits of 6.10 in 8-bit mode with a 162 MHz input signal. Key aspects of the ADC include double sampling to relax amplifier settling times, redundant sign digit correction to compensate comparator offsets, and a two-stage op-amp design to provide sufficient gain and signal headroom given the low 1.2V supply voltage. Measured performance meets the requirements for medium resolution and sampling rate ADCs in modern synthetic aperture radar systems.
This paper presents an improved hardware acceleration scheme for Java method calls in the REALJava coprocessor. The strategy is implemented in an FPGA prototype and allows for measuring real performance increases. It validates the coprocessor concept for accelerating Java bytecode execution in embedded systems with limited CPU performance and memory availability. The coprocessor architecture is highly modular, separating communication from the execution core to improve reusability and allow for system scalability.
The document summarizes developments made to a System on Chip (SoC) to support higher order QAM modulation for wireless systems operating at 38 GHz. Key developments include:
1) Increasing the resolution of analog-to-digital converters and digital-to-analog converters from 8-10 bits to 10-12 bits to support 64QAM modulation.
2) Design improvements to suppress internal clock jitter to less than ±50 picoseconds to enable effective operation with higher resolution converters.
3) Development of a prototype SoC that enables 64QAM modulation, with an architecture that supports up to 256QAM, and achieves an effective throughput of 1 Gbps.
1) Current-steering DACs often have non-linearity due to signal-dependent output impedance, which causes 2nd-order distortion.
2) When used for digital IF generation rather than direct up-conversion, the DAC output contains tones at the desired IF frequency and its harmonics/images.
3) The dominant source of distortion is mixing between the output voltage and digital input signal, generating intermodulation products. Shorting unwanted tones at the DAC output could improve linearity.
The document describes a high-resolution time-to-digital converter (TDC) implemented in a 90nm CMOS process. It uses two gated ring oscillators (GROs) as delay lines in a Vernier structure to achieve both a high time resolution and first-order noise shaping. The TDC achieves less than 10ps coarse resolution, consumes 3.6mA from a 1.2V supply, and occupies an active area of 0.18mm by 0.15mm. Simulation results show the quantization noise is pushed to high frequencies, improving the in-band noise performance for applications like all-digital phase-locked loops.
This document describes novel multi-threshold voltage level converters that minimize power consumption without compromising speed. Conventional feedback-based level converters rely on feedback circuits that cause slow response times and short circuit currents. The novel converters proposed use multiple transistor threshold voltages to directly drive high voltage gates from low voltage signals without static currents. When used in an integrated circuit, the multi-threshold converters decrease power by 47% and optimize delay by 50% compared to feedback converters in a 0.18-μm technology.