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ch00-1-introduction.pdf
1. Applications and Trends of ICs
Jin-Fu Li
Advanced Reliable Systems (ARES) Laboratory
Department of Electrical Engineering
National Central University
Taoyuan, Taiwan
2. Global Semiconductor Sales by Month (89-21)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
Source: Semiconductor Industry Association (SIA)
PC
3C
Smart
Handheld
AIoT
3. AIoT
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
AIoT
Algorithm Infrastructure
Artificial Intelligence Internet of Things
4. AIoTs
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
Smart Cars
Smart Energy
Smart Home
Smart Appliances
Smart Control
Smart Lighting
….
Smart Health
5. A Generic IoT Topology
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
Source: B. Krysiak, STMicroelectronics
6. System-on-Chip (SOC)
A product class and design style that integrates technology and design elements
from other system driver classes (microprocessor unit, embedded memory,
analog/mixed-signal component—as well as reprogrammable logic) into a wide
range of high-complexity, high-value semiconductor products (ITRS 2011)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
7. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
Fundamental Elements of Electronic Systems
Computation
Data (Content) Communication
Processor (multi-core architecture)
Memory
Interface; Bus; Network
8. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
Conventional Computer Architecture
Main Memory System
Von Neumann Architecture
Input/Output
Arithmetic
and
Logic Unit
Operational
Registers
Program
Counter
Control Unit
Data/Instruction
Address
Central Processing Unit
9. Multi-core chip architecture
Use multiple identical cores to design a chip
Network-on-chip communication infrastructure
Multiple point-to-point data links interconnected by switches (i.e., routers)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
Typical SOC Chip Architecture
Source: IEEE Computer, 2005.
DDR2
Controller
DDR2
Controller
μ
Engine
Source: IEEE Micro, 2007.
RAM unit
Compute unit
14. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
Example: SPARC (JSSC, 2011)
Process: TSMC 40nm
Metal layers (Cu): 11
Transistor types: 4
# of Cores: 16
6MB L2 cache
Die area: 377mm2
# of pins: 2117
15. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
The Bit Picture ─ Gap Between Computing & Data
16. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
The Bit Picture ─ Power
Sources: J. Lunteren, IBM
(refer to S. Borkar, “Exascale computing – a fact or a fiction?,” IPDPS, 2013)
Sources: J. Lunteren, IBM
(refer to R. Nair, “Active Memory Cube,” 2nd Workshop on Near-
Data Processing, 2014)
Sources: ITRS 2011
17. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
Conventional Computing Architecture
Processor Main Memory
Bottleneck
(Data Width & Latency)
Processor Main Memory
Cache
Source: H. Kim, et al.,
MEMSYS’15
18. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
Near Memory Computing & Computing in Memory
Overcome the memory wall & power wall
◼ Bring computation closer to the data
◼ Reduce power-expensive data transfer
Approaches
◼ Near memory computing (NMC)
◼ Computing in memory (CIM)
Processor Memory
computing
computing
Computing in Memory (PIM)
Near Memory Computing (NMC)
3D Integration Technology
19. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
What will you learn from this course?
Source: T. Kurafuji, et al., JSSC 2011
1. Low-power design
2. Design-for-test
Infrastructure
Subsystem
Subsystem
Chip Architecture
