2. 2
Architecture
Chipset Model: core (Ivy Bridge) DRAM controller
Code name core Die size(nm) Date
released
Arrandale 2 32 Jan 2010
Sandy Bridge 2 32 Fab 2011
Ivy bridge 2 22 May 2012
Haswell 4 22 June 2013
Haswell 2 22 June 2013
5. 5
Classification of processor on basis of
Flynn’s taxonomy
• The four classifications defined by Flynn are
based upon the number of concurrent
instruction (or control) and data streams
available in the architecture
6. 6
Classifiations
• Single intruction Single Data Stream (SISD)
• Single instruction multiple data stream (SIMD)
• Multiple instruction single data stream (MISD)
• Multiple instruction multiple data steam (MISD)
11. 11
Hyper Threading Technology
• Processor contains two execution units that
contain a complete set of registers capable of
running softwares independently or concuently.
13. 13
Flops
In late 1996 Intel's ASCI Red was the world's first
computer to achieve one TFLOP and beyond,
• and “was supercomputing’s high-water mark in
longevity, price, and performance.
15. 15
Multiplier
• CPU multiplier is clock ratio speed b/w FSB and
CPU
• Multiplier
• Unit 1: 31*
• Unit 2: 29*
• Unit 3: 31*
• Unit 4: 31*
16. 16
Co-Processor/FPU
• Floating point unit(FPU): part of computer
designed to carry out opeartions on floating
point numbers.
Microprocessor Coprocessor
8086/8088 8087
80186/80188 808187
80286 80287
80386 80387
80486SX 80487SX
80586 Bilitin into processor
17. 17
Supported technologies
• MMX: (single instruction multiple data)
Instruction set.
• SSE: Streaming SIMD extensions
• SSSE3 was first introduced with Intel processors
based on the Core microarchitecture
