9. CODE MORPHING MECHANISM
VLIW Processor Core
Code Morphing Software
x86 OS/BIOS
x86 Applications
A dynamic translation System
10. CONVETIONAL CPU
• Use hardware to create and dispatch micro
ops that can be executed in parallel leading to
making them less power efficient
X86 INSTRUCTION
11. ARCHITECTURE OF CRUSOE
L1 INSTRUCTION
CACHE
64 Kb
L1 DATA CACHE
64Kb
BUS
INTERFACE
DDR SDRAM
CONTROLLER
UNIFIED TLB
256 ENTRIES
SERIAL ROM
INTERFACE
CPU CORE
INTEGER UNIT
FLOATING POINT UNIT
MMU
MULTIMEDIA UNIT
L2 Web CACHE
256 Kb
PCI CONTROLLER
SDR SDRAM
CONTROLLER
12. VLIW Technology
The compiler determines which instruction can be
run concurrently.
The compiler generates grouped independent
primitive instruction executable in parallel.
CRUSOE CORE
13. LONGRUN:POWER MANAGEMENT
• Typical Approach 1: Switch off processor quickly to
save power (Can give glitches)
• Typical Approach 2: Change clock rate by
suspending processor and restarting
• Crusoe 1: Adjust clock rate dynamically, without
suspension
• Crusoe 2: Adjust voltage level
• Result: Cubic power reduction, up to 30%.
15. A revolutionary innovation
dies…
• Optimization techniques could be tailored to create
different target architectures.
• Workstation/Server chips were hinted at in the
documentation.
• A whole new family of mobile phone processors
unlike the odds of Nvidia’s Tegra™ and Qualcomm’s
Snapdragon™ series