Digital_Electronics_Basics.pdf

Digital Electronics Basic
Concepts
Digital Electronics
Internshala Trainings

NUMBER SYSTEM

Numbers Every number system is associated with a base or radix
The decimal system has a base of 10 and uses symbols
(0,1,2,3,4,5,6,7,8,9) to represent numbers
5 4 3 2 1 0
5 4 3 2 1 0 5 4 3 2 1 0
( )r
a a a a a a a r a r a r a r a r a r
= + + + + +
A positional notation is commonly used to express numbers
3 2 1 0
10
(2009) 2 10 0 10 0 10 9 10
=  +  +  + 
An octal number system has a base 8 and uses symbols (0,1,2,3,4,5,6,7)
3 2 1 0
8
(2007) 2 8 0 8 0 8 7 8
=  +  +  + 
2 1 0 1 2
10
(123.24) 1 10 2 10 3 10 2 10 4 10
− −
=  +  +  +  + 
What decimal number does it represent?
1 0
8
(2007) 2 512 0 64 0 8 7 8 1033
=  +  +  +  =

A hexadecimal system has a base of 16
3 2 1 0
10
(2 9) 2 16 16 16 9 16
BC B C
=  +  +  + 
Number Symbol
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 A
11 B
12 C
13 D
14 E
15 F
How do we convert it into decimal number?
1 0
10
(2 9) 2 4096 11 256 12 16 9 16 11209
BC =  +  +  +  =

A Binary system has a base 2 and uses only two symbols
0, 1 to represent all the numbers
3 2 1 0
2
(1101) 1 2 1 2 0 2 1 2
=  +  +  + 
Which decimal number does this correspond to ?
1 0
2
(1101) 1 8 1 4 0 2 1 2 13
=  +  +  +  =
1 1 0 1 . 1 0 0 1
23
22
21 20
2-1 2-3
2-2
2-4
20
1
21 2
22 4
23 8
24 16
25 32
26 64
27 128
28 256
29 512
210 1024(K)
220 1048576(M)
2-1 2-2 2-3 2-4 2-5 2-6
0.5 0.25 0.125 0.0625 0.03125 0.015625

1 1 0 0 1 = ?
Developing Fluency with Binary Numbers
25
1100001 = ? 64+32+1=97
0.101 = ? 0.5+0.125=0.625
11.001 = ? 3+0.125=3.125

Converting decimal to binary number
Convert 45 to binary number
10 1 0
(45) .......
n n
b b b
−
=
1 1
1 1 0
45 2 2 ....... 2
n n
n n
b b b b
−
−
= + +
Divide both sides by 2
1 2 0
1 1 0
45
22.5 2 2 ....... 2 0.5
2
n n
n n
b b b b
− −
−
= = + + 
1 2 0
1 1 0
22 0.5 2 2 ....... 2 0.5
n n
n n
b b b b
− −
−
+ = + + + 
0 1
b
 =

1 2 0
1 1 0
22 0.5 2 2 ....... 2 0.5
n n
n n
b b b b
− −
−
+ = + + +  0 1
b
 =
1 2 1 0
1 2 1
22 2 2 ....... 2 2
n n
n n
b b b b
− −
−
= + +
2 3 0
1 2 1
22
11 2 2 ....... 2 0.5
2
n n
n n
b b b b
− −
−
= = + +  1 0
b
 =
2 3 1 0
1 3 2
11 2 2 ...... 2 2
n n
n n
b b b b
− −
−
= + + +
3 4 0
1 3 2
5.5 2 2 ...... 2 0.5
n n
n n
b b b b
− −
−
= + + + 2 1
b
 =
3 4 1 0
1 4 3
5 2 2 ...... 2 2
n n
n n
b b b b
− −
−
= + +

3 4 1 0
1 4 3
5 2 2 ...... 2 2
n n
n n
b b b b
− −
−
= + +
4 5 0
1 4 3
2.5 2 2 ...... 2 0.5
n n
n n
b b b b
− −
−
= + + 3 1
b
 =
4 5 1 0
1 5 4
2 2 2 ...... 2 2
n n
n n
b b b b
− −
−
= + +
5 6 0
1 5 4
1 2 2 ...... 2 0.5
n n
n n
b b b b
− −
−
= + + 4 0
b
 =
5 1
b
 =
10 5 4 3 2 1 0
(45) 101101
b b b b bb
= =

Method of successive division by 2
45
22 1
remainder
11 0
5 1
2 1
1 0
0 1
45 = 1 0 1 1 0 1

Convert (153)10 to octal number system
10 1 0 8
(153) ( ....... )
n n
b b b
−
=
1 1
10 1 1 0
(153) 8 8 ....... 8
n n
n n
b b b b
−
−
= + +
1 2 0 0
1 1
153
19.125 8 8 ....... 8
8 8
n n
n n
b
b b b
− −
−
= = + + 0
0.125
8
b
 = 0 1
b
 =
153
19 1
remainder
2 3
0 2
153 = (231)8

Convert (0.35)10 to binary number
10 1 2 3
(0.35) 0. ....... n
b b b b
− − − −
=
1 2
1 2
0.35 0 2 2 ....... 2 n
n
b b b
− − −
− − −
= + + +
How do we find the b-1 b-2 …coefficients?
Multiply both sides by 2
1 1
1 2
0.7 2 ....... 2 n
n
b b b
− − +
− − −
= + + 1 0
b−
 =
1 2 1
2 3
0.7 2 2 ....... 2 n
n
b b b
− − − +
− − −
= + +

1 2 1
2 3
0.7 2 2 ....... 2 n
n
b b b
− − − +
− − −
= + +
Multiply both sides by 2
1 2
2 3
1.4 2 ....... 2 n
n
b b b
− − +
− − −
= + +
2 1
b−
 =
Note that ½+1/4+1/8+……1
1 2 2
3 4
0.4 2 2 ....... 2 n
n
b b b
− − − +
− − −
= +
1 3
3 4
0.8 2 ....... 2 n
n
b b b
− − +
− − −
= + 3 0
b−
 =

0 .
0 . 25
125
5
1. 0
0.125 = (.001)2
x2
x2
0 .
x2
0.125 = ?
0.8125 = ?
0 .
1 . 625
8125
25
0. 5
x2
x2
1 .
x2
1. 0
x2
0.8125 = (.1101)2

Binary numbers
1011000111
Binary digit = bit
Least significant
bit or LSB
Most significant bit or MSB
This is a 10 bit number
decimal 2bit 3bit 4bit 5bit
0 00 000 0000 00000
1 01 001 0001 00001
2 10 010 0010 00010
3 11 011 0011 00011
4 100 0100 00100
5 101 0101 00101
6 110 0110 00110
7 111 0111 00111
8 1000 01000
9 1001 01001
10 1010 01010
11 1011 01011
12 1100 01100
13 1101 01101
14 1110 01110
15 1111 01111
N-bit binary number can
represent numbers from 0 to 2N
-1

Converting Binary to Hex and Hex to Binary
Number Symb
ol
0(0000) 0
1(0001) 1
2(0010) 2
3(0011) 3
4(0100) 4
5(0101) 5
6(0110) 6
7(0111) 7
8(1000) 8
9(1001) 9
10(1010) A
11(1011) B
12(1100) C
13(1101) D
14(1110) E
15(1111) F
7 6 5 4 3 2 1 0 1 0
( ) ( , )
b Hex
b b b b b b bb h h
=
7 6 5 4 3 2 1 1
7 6 5 4 3 2 1 0 1 0
2 2 2 2 2 2 2 16
b b b b b b b b h h
+ + + + + + = +
3 2 1 4 3 2 1 1
7 6 5 4 3 2 1 0 1 0
( 2 2 2 )2 ( 2 2 2 ) 16
b b b b b b b b h h
+ + + + + + = +
h1 h0
(10110011) (1011)(0011) ( 3)
b Hex
B
= =
(110011) (11)(0011) (33)
b Hex
= =
( ) (1110)(1100) (11101100)
Hex b
EC = =

Binary Addition/Subtraction
0
0
0
0
1
1 1
1
1
1
0
1 0
1
1
1
1 1
1 0 1
1 1 0
1 0 1 1
1 1 0 1
1 1 0 1 1
+ 1 1 1 0

Complement of a number
Decimal system:
9’s complement
10’s complement
9’s complement of n-digit number x is 10n -1 -x
10’s complement of n-digit number x is 10n -x
9’s complement of 85 ? 2
10 1 85
− − 99 85 14
− =
9's complement of 123 = 999 123 876
− =
10's complement of 123 = 9's complement of 123+1 877
=

Complement of a binary number
Binary system:
1’s complement
2’s complement
1’s complement of n-bit number x is 2n -1 -x
2’s complement of n-bit number x is 2n -x
1’s complement of 1011 ? 4
2 1 1011
− − 1111 1011 0100
− =
1's complement of 1001101 = ?
0110010
1’s complement is simply obtained by flipping a bit (changing 1 to 0 and 0 to 1)

2's complement of 1010 = 1's complement of 1010+1 0110
=
2's complement of 110010 =
001110
Leave all least significant 0’s as they are, leave first 1 unchanged and then flip
all subsequent bits
1011 0101
→
101101100 010010100
→

Advantages of using 2’s complement
Adder
x1
x2
S
CY
Can we carry out Y = X1 – X2 using such an adder?
x2
Adder
2's Complement
Y = S if Sign = 0
Y = 2's Complement of S if Sign = 1
S
Y
x1
x1,x2: N bit numbers
Sign
Sign = 0 for psotive numbers
= 1 for negative numbers
CY
2
2N
x
− 1 2
( , ) 2N
CY S x x
= + −
Note that carry will be there only if x1 – x2 is positive as 2N is N+1 bits (1
followed by N zeros) Internshala Trainings

Advantages of using 2’s complement
x2
Adder
2's Complement
Y = S if Sign = 0
S
Y
x1
Sign
CY
2
2N
x
− 1 2
( , ) 2N
CY S x x
= + −
Note that carry will be there only if x1 – x2 is positive as 2N is N+1 bits (1
followed by N zeros)
A zero carry implies a negative number whose magnitude (x2 – x1) can be found
as follows:
1 2
2N
S x x
= + −
1 2 2 1
2'scomplement of 2 ( 2 )
N N
S x x x x
= − + − = −

Adder
2's Complement
Y = S if Sign = 0
S
Y
Sign
CY
x1=1010
x2=0110
Example
10
6
1010
1 0 1 0
+ 1 0 1 0
1 0 1 0 0
0100
1 0
0100

Adder
2's Complement
Y = S if Sign = 0
S
Y
Sign
CY
x1=0110
x2=1010
Example
6
10
0110
0 1 1 0
+ 0 1 1 0
1 1 0 0
1100
0 1
0100
It makes sense to use adder as a subtractor as well provided additional circuit
required for carrying out 2’s complement is simple

Subtraction using 10’s complement
x2
Adder
S
Y
x1
Sign
CY
x1,x2: N digit numbers
10's Complement
Y = S if Sign = 0
8
3
10-3=7
1
5
5
0
This way of subtraction would make sense only if subtracting a number x2
from 10N is much simpler than directly subtracting it directly from x1

Representing positive and negative binary numbers
One extra bit is required to carry sign information. Sign bit = 0
Represents positive number and Sign bit = 1 represents negative number
decimal Signed
Magnitude
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
-0 1000
-1 1001
-2 1010
-3 1011
-4 1100
-5 1101
-6 1110
-7 1111
decimal Signed 1’s
complement
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
-0 1111
-1 1110
-2 1101
-3 1100
-4 1011
-5 1010
-6 1001
-7 1000
decimal Signed 2’s
complemen
t
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
-1 1111
-2 1110
-3 1101
-4 1100
-5 1011
-6 1010
-7 1001

If we represent numbers in 2’s complement
form carrying out subtraction is same as addition
x2
Adder
2's Complement
Y = S if Sign = 0
S
Y
x1
Sign
CY
Adder
S
x1
x2
x1,x2: N bit numbers in 2's complement
CY
Answer is in 2’s
complement form

Example
Adder
S
x1
x2
x1,x2: N bit numbers in 2's complement
CY
0 1 0 1
+ 0 0 1 0
0 1 1 1
+ 5
+ 2
+7
+ 5
- 2
+3
0 1 0 1
+ 1 1 1 0
0 0 1 1
- 5
+ 2
- 3
1 0 1 1
+ 0 0 1 0
1 1 0 1
2’s complement is 0011 = 3
- 5
- 2
- 7
1 0 1 1
+ 1 1 1 0
1 0 0 1
2’s complement is 0111 = 7

BOOLEAN ALGEBRA

Boolean Algebra
Algebra on Binary numbers
A variable x can take two values {0,1} 0
False
No
Low voltage
1
True
Yes
High voltage
Basic operations:
1 2
AND: y = x . x
Y is 1 if and only if both x1 and x2 are 1, otherwise zero
x1 x2 y
0 0 0
0 1 0
1 0 0
1 1 1
Truth Table

Basic operations:
1 2
OR: y = x + x
Y is 1 if either x1 and x2 is 1. Or y= 0 if and only if both variables are zero
x1 x2 y
0 0 0
0 1 1
1 0 1
1 1 1
NOT: y = x
y
x
1
1
0
0

Boolean Algebra
Basic Postulates
P1: x + 0 = x
P2: x + y = y + x
P3: x.(y+z) = x.y+x.z
P4: x + x = 1
P1: x . 1 = x
P2: x . y = y . x
P3: x+y.z = (x+y).(x+z)
P4: x . x = 0
Basic Theorems
T1: x + x = x
T2: x + 1 = 1
T3: ( x ) = x
T4: x + (y+z) = (x+y)+z
T5 (x+y) = x . y (DeMorgan's theorem)
T6: x+ x.y = x
T1: x . x = x
T2: x . 0 = 0
T4: x . (y.z) = (x.y).z
T5 (x.y) = x + y (DeMorgan's theorem)
T6: x.( x+y) = x

P1: x + 0 = x
P2: x + y = y + x
P3: x.(y+z) = x.y+x.z
P4: x + x = 1
P1: x . 1 = x
P2: x . y = y . x
P3: x+y.z = (x+y).(x+z)
P4: x . x = 0
Proving theorems
Prove T1: x + x = x
x + x = (x+x). 1 (P1)
= (x+x). (x+x) (P4)
= x + x.x (P3)
= x + 0 (P4)
= x (P1)
Prove T1: x . x = x
x . x = x.x+ 0 (P1)
= x.x + x.x (P4)
= x . (x+x ) (P3)
= x . 1 (P4)
= x (P1)

Prove : x + 1 = 1
Proving theorems
x + 1 = x+(x+ x)
= (x+x)+ x
= x + x
= 1
P1: x + 0 = x
P2: x + y = y + x
P3: x.(y+z) = x.y+x.z
P4: x + x = 1
P1: x . 1 = x
P2: x . y = y . x
P3: x+y.z = (x+y).(x+z)
P4: x . x = 0
x + x .y = x
= x . 1 + x. y
= x. (1+ y)
= x . 1
=x
DeMorgan’s theorem
1 2 3 1 2 3
(x x x ....) x . x .x .
+ + + =
1 2 3 1 2 3
(x . x . x .....) ( x + x x +.....)
= +
x + x .y = x+y
= (x + x ). (x+ y)
= 1. (x+ y)
= x + y

Simplification of Boolean expressions
1 2 2 3
(x .x x .x ) ?
+ =
1 2 3 1 2 3
(x x x ....) x . x .x .
+ + + =
1 2 3 1 2 3
(x . x . x .....) ( x + x x +.....)
= +
1 2 2 3
(x x ) . (x + x )
= +
1 2 1 3 2 3
x . x x . x x . x
= + +

Function of Boolean variables
x1
x2
y
y
x
x1 x2 y
0 0 0
0 1 1
1 0 0
1 1 0
2
y= x
Y = 1 when x1 is 0 and x2 is 1
1 2
y= .
x x
Boolean expression

Obtaining Boolean expressions from truth Table
x1 x2 y
0 0 1
0 1 0
1 0 0
1 1 0
1 2
y= .
x x
x1 x2 y
0 0 0
0 1 0
1 0 1
1 1 0
1 2
y= .
x x
x1 x2 y
0 0 1
0 1 0
1 0 0
1 1 1
1 2
.
x x
1 2
.
x x
1 2 1 2
y= . .
x x x x
+

x1 x2 y
0 0 0
0 1 1
1 0 1
1 1 0
1 2 1 2
y= . .
x x x x
+
Instead of writing expressions as sum of terms that make y equal to 1, we
can also write expressions using terms that make y equal to 0
x1 x2 y
0 0 1
0 1 1
1 0 1
1 1 0
1 2 1 2 1 2
y= . . .
x x x x x x
+ +
1 2
y=x x
+

x1 x2 y
0 0 1
0 1 0
1 0 1
1 1 1
1 2
y=x x
+
x1 x2 y
0 0 0
0 1 1
1 0 1
1 1 1
1 2
y=x x
+
x1 x2 y
0 0 0
0 1 1
1 0 1
1 1 0
1 2
x x
+
1 2
x x
+
1 2 1 2
y=(x ).( )
x x x
+ +

1 2 3 1 2 3 1 2 3 1 2 3
y= . . . . . . . .
x x x x x x x x x x x x
+ + +
y
x1 x2 x3
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
1 2 3 1 2 3 1 2 3 1 2 3
y=( ).( ).( ).( )
+ + + + + + + +
Sum of Products (SOP) form
Product of Sum (POS) form

IMPLEMENTATION OF
BOOLEAN EXPRESSIONS

Implementing Boolean expressions
Elementary Gates
1 2
AND: y = x . x
x1
x2
y
AND
Why call it a gate?
x1
AND y = 0
0
Gate is closed
x1
AND
1
y = x1
Gate is open
1 2
OR: y = x + x
x1
x2
y
OR
NOT: y = x y
x

1 2
NAND: y = x . x
x1
x2
y
NAND
x1
x2
AND
x1x2
x1x2
1 2
NOR: y = x + x
x1
x2
OR
x1+x2
x1+x2
x1
x2
y
NOR

1 2 1 2 1 2
XOR: y = x x =x . .
x x x
 +
x1 x2 y
0 0 0
0 1 1
1 0 1
1 1 0
Y is 1 if only one variable is 1 and the other is zero
x2
x1
x1 x1x2
x1x2
x2
y x1
x2
y
XOR
1 2 1 2 1 2
XNOR: y =x x = x . .
x x x
+
Y is 1 if only both variables are either 0 or 1
x1
x2
y
XNOR
1 2 1 2
y =x x =x x


Gates with more than 2 inputs
1 2 3
AND: y = x . x . ...
x y
AND
x1
x2
x3
1 2 3
OR: y = x + x ....
x
+ +
x1
x2
x3
y
1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
XOR: y =x x x = x . . . . . . .
x x x x x x x x x x x
  + + +
Y = 1 only if odd number of inputs is 1

Implementing Boolean expressions using gates
. . . . . . . .
S x y z x y z x y z x y z
= + + +
. . .
C x y x z y z
= + +
x
y
z
S
C
y
y
z
y
z
x
x
x
y
y
z
z
z
S
x
x y z
x y z
x y z
x y z
x
y
y
z
z
x
C

Implementing gates using Switches
x
SN
Voltage controlled Switch
SN:
Switch is closed if voltage x is HIGH
Switch is open if voltage x is LOW
x
SP
Voltage controlled Switch
SP:
Switch is closed if voltage x is LOW
Switch is open if voltage x is HIGH
We have seen earlier (in class 12) that transistors act as switches !

SN
SP
VDD = 5V
x y
x
SN
Switch is closed if voltage x is HIGH
Switch is open if voltage x is LOW
Switch is closed if voltage x is LOW
Switch is open if voltage x is HIGH
x
SP
LOW
closed
open
HIGH
0
1
y
x
NOT gate

SN
SP
x1
SN
x1
x2
SP
x2
y
VDD = 5V
NAND Gate
1 2
NAND: y = x . x
y
x2
x1
LOW HIGH
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH HIGH
LOW
LOW

NOR Gate
1 2
NOR: y = x + x
SP
x1
SN
SP
x2
SN
y
x1 x2
VDD = 5V
y
x2
x1
LOW HIGH
HIGH
HIGH
LOW
LOW
HIGH HIGH
LOW
LOW
LOW
LOW

x
y
y
z
z
x
C
Design Overview a b c S CY
0 0
0 0
0 0
1
0 1 1
0 0
1
0 1
1
0
1
1
1
1 1
0 0
0
1 1
0
0
1
1
0
1 0
0
0
1
1
1
1
Full Adder
b
c
S
CY
a
. . . . . . . .
S x y z x y z x y z x y z
= + + +
. . .
C x y x z y z
= + +
y
y
z
y
z
x
x
x
y
y
z
z
z
S
x
x y z
x y z
x y z
x y z
SN
SP
x1
SN
x1
x2
SP
x2
VDD = 5V
SP
SN
y

SOP AND POS
REPRESENTATIONS

Representation of Boolean Expressions
x y min term
0 0 x . y m0
0 1 x . y m1
1 0 x . y m2
1 1 x . y m3
0 0 0
0 1 1
1 0 1
1 1 0
x y f1
1
f = . .
x y x y
+ 1 1 2
f = m m
+ 1
f = (1,2)

2
f = (0,2,3) ?
=
 2
f = . . .
x y x y x y
+ +
A minterm is a product that contains all the variables used in a function

Three variable functions
y z min terms
0 0 0 x . y . z
0 0 1 x . y . z
0 1 0 x . y . z
0 1 1 x . y . z
1 0 0 x . y . z
1 0 1 x . y . z
1 1 0 x . y . z
1 1 1 x . y . z
x
m0
m1
m2
m3
m4
m5
m6
m7
2
f = (1,4,7) ?
=

2
f = . . . . . .
x y z x y z x y z
+ +

Product of Sum Terms Representation
0 0 0
0 1 1
1 0 1
1 1 0
x y f1 x y
0 0 x + y M0
0 1 x + y M1
1 0 x + y M2
1 1 x + y M3
Max term
F1 = (x+y)(x’ + y’) = M0.M3 = ∏M0M3

y z
x Max. terms
M0
M1
M2
M3
M4
M5
M6
M7
0 0 0 x + y + z
0 0 1 x + y + z
0 1 0 x + y + z
0 1 1 x + y + z
1 0 0 x + y + z
1 0 1 x + y + z
1 1 0 x + y + z
1 1 1 x + y + z
1
f = (1,5,7) ?
 =
2
f =(x ).( ).( )
y z x y z x y z
+ + + + + +

Simplification of Boolean Expressions
y
x1 x2 x3
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
1 2 3 1 2 3 1 2 3 1 2 3
y= . . . . . . . .
+ + +
y= (1,3,5,7)

y
x1
x2
x3
x1
x2
x3
x2
x3
x1
x2
x3
x1
Simplification of Boolean expression yields : y = x3 !! which does not
require any gates at all !

Goal of Simplification
1 2 3 1 2 3 1 2 3 1 2 3
y= . . . . . . . .
+ + +
y
x1
x2
x3
x1
x2
x3
x2
x3
x1
x2
x3
x1
Goal of simplification is to reduce the complexity of gate circuit. This requires
that we minimize the number of gates. Since number of gates depends on
number of minterms, one of the goals of simplification is to minimize the
number of minterms in SOP expression

1 2 3 1 2 3 1 2 3 1 2 3
y= . . . . . . . .
+ + +
y
x1
x2
x3
x1
x2
x3
x2
x3
x1
x2
x3
x1
1 3 1 2 3 1 2 3
y= . . . . .
x x x x x x x x
 + +
y
x1
x2
x3
x2
x3
x1
x1
x3
This circuit is simpler not just because it uses 4 gates instead of 5 but also
because circuit-2 uses one 2-input and three 3-input gates as compared to five
3-input gates used in circuit-1

Goal of Simplification
1. Minimize number of product terms
2. Minimize number of literals in each term
In the SOP expression:
Simplification Minimization


Minimization
1 2 3 1 2 3 1 2 3 1 2 3
y= . . . . . . . .
+ + +
1 3 2 2 1 3 2 2
y= . .( ) . .( )
x x x x x x x x
+ + +
1 3 1 3
y= . .
x x x x
+
1 1 3
y=( ).
x x x
+
3
y= x
Principle used: x + x = 1

f = . . .
x y x y x y
+ +
Apply the Principle: x + x = 1 to simplify
f = .( ) .
x y y x y
+ +
f = .
x x y
+
How do we simplify further?
f = . . . . . . .
x y x y x y x y x y x y x y
+ + = + + +
Principle used : x + x = x
f = . . . .
. ( ) ( ).
x y x y x y x y
x y y x x y x y
+ + +
= + + + = +

Simplify
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
1 2 3 4 1 2 3 4
. . . . . . . . . . . .
. . . . . .
f x x x x x x x x x x x x x x x x
x x x x x x x x
= + + + +
+
Principle: x + x = 1 and x + x = x
Need a systematic and simpler method for applying these two principles
Karnaugh Map (K map) is a popular technique for carrying out simplification
It represents the information in problem in such a way that the two
principles become easy to apply

KARNAUGH MAPS

K-map representation of truth table
x y min term
0 0 x . y m0
0 1 x . y m1
1 0 x . y m2
1 1 x . y m3
0
1
1
0
m0
m3
x
y
m2
m1
0 0 0
0 1 1
1 0 1
1 1 0
x y f1
0
1
1
0
x
y
0 1
1 0

2
f = (0,2,3)

0
1
1
0
x
y
1
1 0
0
f = . .
x y x y
+

3-variable K-map representation
y z min terms
0 0 0 x . y . z
0 0 1 x . y . z
0 1 0 x . y . z
0 1 1 x . y . z
1 0 0 x . y . z
1 0 1 x . y . z
1 1 0 x . y . z
1 1 1 x . y . z
x
m0
m1
m2
m3
m4
m5
m6
m7
yz
x 00 01 11
0
1
10
m0 m1 m3 m2
m4 m5 m6
m7
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
x y z f
yz
x 00 01 11
0
1
10
0 1 1 0
0 1 1 0

yz
x 00 01 11
0
1
10
1 0
0 1 1 0
0
1
f = . . . . . . . .
x y z x y z x y z x y z
+ + +

w x y z
0 0 0
0 0 0 1
0
min terms
m0
m1
0 0 1 0 m2
0 0 1
1 m3
1 1 1 0 m14
1 1 1 1 m15
4-variable K-map representation
yz
wx 01 11
11
01
00
00 10
10
0 1 3 2
4 5 7 6
12 13 15 14
8 9 10
11
yz
1 0
1
wx 01 11
11
01
00 0
00 10
0 1 1 0
1 0 1
0
1 0 0
0
10
f =w. . . w. . . . . . . . .
. . . . . . . . .
x y z x y z w x y z w x y z
w x y z w x y z w x y z
+ + +
+ + +

Minimization using Kmap
2
f = (2,3)

0
1
1
0
x
y
0
1 1
0
f = . .
x y x y
+
f = .( )
x y y
+
f = x
Combine terms which differ in only one bit position. As a result,
whatever is common remains.

0
1
1
0
x
y
1
0
0 1
f = . .
x y x y
+
f =( . ).
x x y
+ f = y

0
1
1
0
x
y
1 0
1 0
f = y

0
1
1
0
x
y
1
0
0
1
f = x


0
1
1
0
x
y
0 1
1 1
f = . . .
x y x y x y
+ +
f = .( ) .
.
x y y x y
x x y
+ +
= +
f = . .
( ).
x x y x y
x x x y
x y
+ +
= + +
= +
The idea is to cover all the 1’s with as few and as simple terms as possible

yz
x 00 01 11
0
1
10
1 0
0 1 1 0
0
1
3-variable minimization
f = . . . . . . . .
+ + +
.
x z
.
y z
f = . . . .
x y z y z x z
+ +

yz
x 00 01 11
0
1
10
0 1 1 0
1 0
0 1
f = . . . . . . . .
+ + +
.
x z
.
x z
f = . .
x z x z
+

yz
x 00 01 11
0
1
10
1 1
0
0
1 1
0 0
f = . . . . . . . .
+ + +
.
x y
.
x y
f = . .
x y x y
+
f = .( )
x y y x
+ =
yz
x 00 01 11
0
1
10
1 1
0
0
1 1
0 0
x

yz
x 00 01 11
0
1
10
1 1 1 1
0 0 0 0 x
yz
x 00 01 11
0
1
10
1 1
0 0
1 1
0 0
z
yz
x 00 01 11
0
1
10
1
1
0 0
0 0
1
1
z
yz
x 00 01 11
0
1
10
1
1
0 0
1
1 1 1
z
x
f =x z
+

yz
x 00 01 11
0
1
10
0 0
1 1 1
0
0
0
Can we do this ?
Note that each encirclement should represent a single product term. In this
case it does not.
f = . . . . . .
. .
x y z x y z x y z
x y x z
+ +
= +
We do not get a single product term.
In general we cannot make groups of 3 terms.

yz
x 00 01
0
1
0 0
1 1
0
0
0
10 11
0
Can we use kmap with the following ordering of variables?
Can we combine these two terms into a single term ?
f = . . . .
.( . . )
x y z x y z
x y z y z
+
= +
Note that no simplification is possible.
Kmap requires information to be represented

yz
x 00 01
0
1
0
0
0
10 11
0
1 1
0 0
These two terms can be combined into a single term but it is not easy to
show that on the diagram.
f = . . . .
.( ). .
x y z x y z
x y y z x z
+
= + =
Kmap requires information to be represented in such a way that it is easy
to apply the principle 1
x x
+ =

yz
1 0
1
wx 01 11
11
01
00 0
00 10
0 1 1 0
1 0 1
0
1 0 0
0
10
. .
w x z
. .
w y z
. .
w y z
f = . . . . . . . . . . . .
w y z w x z w y z w x y z w x y z
+ + + +
But is this the simplest expression ?

yz
1 0
1
wx 01 11
11
01
00 0
00 10
0 1 1 0
1 0 1
0
1 0 0
0
10
. . . . . . . .
w x y z w x y z w x z
+ =
yz
1 0
1
wx 01 11
11
01
00 0
00 10
0 1 1 0
1 0 1
0
1 0 0
0
10
. . . . . . . .
w x y z w x y z x y z
+ =

yz
1 0
1
wx 01 11
11
01
00 0
00 10
0 1 1 0
1 0 1
0
1 0 0
0
10
. .
w x z
. .
w y z
. .
w y z
f = . . . . . . . . . .
w y z w x z w y z w x z x y z
+ + + +
. .
w x z
. .
x y z
Is this the best that we can do ?

yz
1 0
1
wx 01 11
11
01
00 0
00 10
0 1 1 0
1 0 1
0
1 0 0
0
10
f = . . . .
. . . . . .
w y z w x z
w y z w x z x y z
+ +
+ +
yz
1 0
1
wx 01 11
11
01
00 0
00 10
0 1 1 0
1 0 1
0
1 0 0
0
10
Cover the 1’s with minimum number of terms
f = . . . .
. . . .
w y z w x z
w x z x y z
+ +
+

yz
0
1
wx 01 11
11
01
00 0
00 10
1 0
0 0
1 0 0
10
1
0
0
0 0
1
yz
0
1
wx 01 11
11
01
00 0
00 10
1 0
0 0
1 0 0
10
1
0
0
0 0
1
f = . . . . . .
w x y w x z w y z
+ + f = . . . . . .
w x y w x z x y z
+ +

Groups of 4
yz
0
wx 01 11
11
01
00
00 10
1
0
0
10
1
0
0 0
0
1 1
0 0
1
1
1
.
w x
.
y z
yz
0
wx 01 11
11
01
00
00 10
1
10
0
0 0
0
1
0 0
1
1
0 0
1
1
0
.
x z
.
w z

yz
0
wx 01 11
11
01
00
00 10
10
0
0
0 0
0
1 0 0 1
1 0 0 1
0 0
yz
wx 01 11
11
01
00
00 10
10
0
0 0
0 0
0
1 1
1 1
0 0
0 0
0 0
yz
0
wx 01 11
11
01
00
00 10
10
0 0
0
0 0
1
0 0
1
1 1
0 0
0 0
yz
0
wx 01 11
11
01
00
00 10
10
0 0
0
0 0
1
0
1 1
1
0
0
0
0
0
.
x z .
x z
.
x z
??

Groups of 8
yz
0
wx 01 11
11
01
00
00 10
1
10
0
0
1
0 0
1
1
1
1
1
1
0
0
0 z
yz
0
wx 01 11
11
01
00
00 10
1
10
0
1
0 0
1 1
1 1
1 1
0 0
0 0
x
yz
wx 01 11
11
01
00
00 10
10
1 1
1 1
0 0
0 0
1
1
1
1
0 0
0 0
z
yz
wx 01 11
11
01
00
00 10
10
1
1
1
1
0 0
0 0
1 1
1 1
0 0
0 0
x

Examples
yz
wx 01 11
11
01
00
00 10
1
10
0
1
0
1 1
1 1
1 1
0
0 0
1 1
1
yz
wx 01 11
11
01
00
00 10
1
10
0
0
1 1
1 1
1 1
0
0 0
1 1
1
0

Don’t care terms
0 0 0
0 0 0 1
0
0 0 1 0
0 0 1
1
a b c d
1 1
0
0 1
0 1
1 0 0
1 0
1 0
1
0
1 0 0 0
0 0 1
0 1 0
0 1
1
1 1
1
1
1 0 0
1 0
1 0
1
1
1
1
1
1
1
1
0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0
y0y1y2y3y4y5y6y7y8y9
0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0
x x x x x x x x x x
x x x x x x x x x x
x x x x x x x x x x
x x x x x x x x x x
x x x x x x x x x x
x x x x x x x x x x
a
b
c
d
y0
y1
y2
y3
y9
Decimal
Decoder
01 11
11
01
00
00 10
10 0
ab
cd
0 0
0 0 0 0
x x x x
x x
1
0
0
Y3
3 . . .
y a b c d
=

01 11
11
01
00
00 10
10 0
ab
cd
0 0
0 0 0 0
x x x x
x x
1
0
0
Y3
Don’t care terms can be chosen as 0 or 1.
Depending on the problem, we can choose the don’t care term
as 1 and use it to obtain a simpler Boolean expression
3 . .
y b c d
=
Don’t care terms should only be included in encirclements if it helps in
obtaining a larger grouping or smaller number of groups.

Minimization of Product of Sum Terms using Kmap
0
1
1
0
x
y
0 1
1 1
f = . .
( ).
x x y x y
x x x y
x y
+ +
= + +
= +
0
1
1
0
x
y
0 1
1 1
f = x y
+
0
1
1
0
x
y
1
0
0 1
f = y

0
1
1
0
x
y
1 0
1 0
f = y

0
1
1
0
x
y
1
0
0
1
f = x

yz
x 00 01 11
0
1
10
0 1 1 0
1 0
0 1
.
x z
+
x z
+
f =( . ).( )
x z x z
+ + f = . .
x z x z
 +

yz
wx 01 11
11
01
00
00 10
1
10
0
1
0
1
1 1
1 1
0 0
1 1
0
0
0
x y z
+ + x y z
+ +
w y z
+ +
w x
+
f =( ).( ).( ).( )
x y z x y z w y z w x
+ + + + + + +

yz
wx 01 11
11
01
00
00 10
10
1
1
1 1
1
1
0
0 x
x
0
x
x
1
1
1
Example
Obtain the minimized PoS by suitably using don’t care terms
f =( ).( ).( )
x w z x w y y z
+ + + + +

Design Flow
System Description
Truth Table
Boolean Expression
Minimized
Boolean Expression
Gate Netlist
x
y
z
f
system
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
x y z f
f = . . . . . . . .
+ + +
f = . .
x z x z
 +
x
y
y
z
z
x
C

Library of available Gates Cost
Inverter 1
Two input NAND 2
Three input NAND 3
AND-OR-Invert 3
C
AB
Y +
=
y
x1
x2
x3
x1
x2
x3
x2
x3
x1
x2
x3
x1
Mapping of Boolean expression to a Network of
gates available in the library
1 2 3 1 2 3 1 2 3 1 2 3
y= . . . . . . . .
+ + +

IMPLEMENTATION USING
SPECIFIC GATES

Implementation using only NAND gates
.
x x x
= .
x y
.
x y
x
y f = .
x y x y
= +
A SoP expression is easily implemented with NAND gates. f = . . .
a b c d g h
+ +
a
b
c
d
g
h
f
a
b
c
d
g
h
f

a
b
c
d
g
h
f
a
b
c
d
g
h
f
a
b
c
d
g
h
f
There is a one-to-one mapping between AND-OR network and NAND network

Often there is lot of further optimization that can be done
Consider implementation of XOR gate . .
f A B A B
= +
. . . .
( ) ( )
f A B B B A B A A
B A B A A B
= + + +
= + + +

Implementation using only NOR gates
x x x
+ =
x y
+
x y
+
x
y f = .
x y x y
+ =
To implement using NOR gates, it is easiest to start with minimized Boolean
expression in POS form
f =( ).( ).( )
a b c d g h
+ + +

f =( ).( ).( )
a b c d g h
+ + +
a
b
c
d
g
h
f
a
b
c
d
g
h
f
a
b
c
d
g
h
f
There is a one-to-one mapping between OR-AND network and NOR network

To implement SoP expression using NOR gates, determine first the
corresponding PoS expression and then follow the procedure
outlined earlier
Implement f(x,y,z)= . . using NOR gates
x z x z
+
yz
x 00 01 11
0
1
10
0 1 1 0
1 0
0 1 f =( . ).( )
x z x z
 + +
x
x
z
z
f
x
z
f
z
x
Similarly PoS expression can be implemented as NAND network by first
converting it to SoP expression and then following the procedure outlined
earlier

COMBINATIONAL CIRCUIT
DESIGN

Digital Circuits
Combinational Circuits Sequential Circuits
CC
X
Y
W
Output is determined by current
values of inputs only.
X
Z
CC
Storage
elements
Output is determined in general
by current values of inputs and
past values of inputs/outputs as
well.

Design of Complex Combinational circuits
8-bit adder
B(0:7)
A(0:7) S(0:7)
C
C
00...0
A7A6...A0 B7B6...B0 S7S6...S0
00...0 00...0 0
00...1 00...0 00...1 0
00...1 0
00...1
00...0 Truth table has 216 entries
System
Description
Truth
Table
Boolean
expression
Minimized Boolean
expression
Gate
Netlist
This design approach becomes difficult to use

B(0:7)
A(0:7) S(0:7)
8-bit adder
C
1-bit adder
1-bit adder
1-bit adder
A1
A7 B1
B7 A0
B0
S0
C0
S1
C1
S7
C7
Design system as a network of sub-systems that are of
manageable size and can be implemented using the
earlier approach of truth table, minimization etc.
a b c S CY
0 0
0 0
0 0
1
0 1 1
0 0
1
0 1
1
0
1
1
1
1 1
0 0
0
1 1
0
0
1
1
0
1 0
0
0
1
1
1
1
1 1 0 1
1 1 0 1 1
+ 1 1 1 0

General Approach
System
Sub-system-1
Sub-system-2
Sub-system-3
There are certain sub-systems or blocks that are used quite often such as :
1. decoders, encoders
2. Multiplexers
3. Adder/Subtractors, Multipliers
4. Comparators
5. Parity Generators
6. ……..

Decoders
2-to-4 line
decoder
B
A
y3
y0
y1
y2
Maps a smaller number of inputs to a larger set of outputs in general
Active Low
0 0
0
0
1
1 1
1
Y0 Y1 Y2 Y3
0 0
0
1
0 1 0 0
0 0 1 0
0 0 1
0
B A
2-to-4 line
decoder
A
B
y0
y2
y1
y3
0 0
0
0
1
1 1
1
b a Y0 Y1 Y2 Y3
0 1 1
1 1
0
1
0
1
1
1
1
0
1
1 1

M-1
M-2
M-3
M-4
M-2
M-3
M-4
M-1
2-to-4
decoder
Example

B
A
y2
y3
y1
y0
E
2/4
Decoder with Enable Input
Y0 Y1 Y2 Y3
A
B
E
0
0
0
1
1 0 1 0 0
0 0 1 0
0 1
0
1
1
1
1
0
1
1
0
0
x x
1 0 0 0
0 0 0
0
B
A
y2
y3
y1
y0
E
2/4 Y0 Y1 Y2 Y3
A
B
E
0
0
0
1
1 0 1 0 0
0 0 1 0
0 1
0
1
0
1
0
x x
1 0 0 0
0 0 0
0
1
0
0
0
0

B
A
y2
y3
y1
y0
E
2/4
Y0 Y1 Y2 Y3
A
B
E
0
0
0
1
1 0 1 0 0
0 0 1 0
0 1
0
1
1
1
1
0
1
1
0
0
x x
1 0 0 0
0 0 0
0
Decoder: gate Implementation
0 1 2 3
Y =E.B.A ;Y =E.B.A;Y =E.B.A ;Y =E.B.A
B
A
E
Y0
Y1
Y2
Y3
E.B.A
E.B.A
E.B.A
E.B.A

A n to 2n decoder is a minterm generator
x y min term
0 0 x . y m0
0 1 x . y m1
1 0 x . y m2
1 1 x . y m3
B
A
E
Y0
Y1
Y2
Y3
E.B.A
E.B.A
E.B.A
E.B.A
It can be used to implement any combinational circuit
0 0 0
0 1 1
1 0 1
1 1 0
f1
B A
B
A
y2
y1
y0
y3
f
1 E
2/4
1
0
0
1
0
0
1

Implementation of a 3-variable function with a 3-to-8 decoder
A
B
C f
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
B
A
C
y1
y2
y3
y4
y5
y6
y7
y0
E
3/8
f
0
0
0
0
0
1
1
1
1
1
1
1
1
Although it is easy to implement any combinational circuit with this method ,
it is often very inefficient in terms of gate utilization. Note that this method
does not require any minimization.

Implementing larger decoders using simpler ones.
3/8 decoder using 2/4 decoders
B
A
y2
y3
y1
y0
E
2/4
B
A
C
y1
y2
y3
y4
y5
y6
y7
y0
E
3/8
B
A
E
2/4
y4
y5
y6
y7
2/4
E
C
0
How many 2/4 decoders are required to implement a 4/16 decoder ?

A
B
C
E y0 y1 y2 y3 y4 y5 y6 y7
0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
B
A
y2
y3
y1
y0
2/4
E y4
y6
y7
E
A
B
2/4
y5
E
C
0
2/4
Y0 Y1 Y2 Y3
A
B
E
0
0
0
1
1 0 1 0 0
0 0 1 0
0 1
0
1
1
1
1
0
1
1
0
0
x x
1 0 0 0
0 0 0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0

Seven segment decoder
A
B
D
C
7-segment
decoder
(abcdefg)
b
a
c
d
e
f
g
g
a
b
c
d
e
f
a
c
d
f b
e
g
a
c
f
e
g
d
b
a
b
c
d
e
f
g
5
5
5
5
5
0
5

Seven segment decoder
b
a
c
d
e
f
g
A
B
D
C
7-segment
decoder
(abcdefg)
1
1
01 11
11
01
00 0
00 10
0 1 1 0
0
1 0
0
10
BA
DC
0
1
1
1
0

7449 BCD to seven segment decoder
D
C
7-segment
decoder
(abcdefg)
B
A
BL

01 11
11
01
00
00 10
10
d3d2
1
0
d1d0
0
1
Encoders
An encoder performs the inverse operation of a decoder.
4/2
A
B
3
0
2
1
B A
0
0
0 0
0 0 0
0
0
1
1
1
1
0
d3 d0
d1
d2
1
0
0 1
1 0
0
0
0
1
01 11
11
01
00
00 10
10
d3d2
d1d0
0 1
0
1
2 0
A d d
=
1 0
B d d
=

M-1
M-2
M-3
M-4
M-2
M-3
M-4
M-1
2-to-4
decoder
M-2
M-3
M-4
M-1
4/2
encoder
2/4
decoder

Priority Encoders
Resource
4:1 MUX
x y
printer
D0
D1
D2
D3
Priority is 3,2,1,0 with user 3
having the highest priority
X, Y have to be determined
based on this priority order and
the requests to use the resource.
0 0
0
0
1 0
0
0
x y
R0 R1 R2
x x
0
R3
0
1
0
0
x 0 1
x x 1 0 1 0
x x 1
x 1 1
01 11
11
01
00
00
10
R3R2
R1R0
0 0 0
1
1 1
1
1
1
1 1
1
1 1
1
1
10
X
R0
R1
R2
R3
priority
Encoder
2 3
x R R
= +
01 11
11
01
00
00
10
R3R2
R1R0
10
Y
0 1 1
0 0 0 0
1 1 1
1 1 1
1
1
1 2 3
y R R R
= +

Gray Codes
decimal Natural
Binary
Gray
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
1-bit change as one goes from
one code word to the next.
0111-1111-1000 0111-0000-1000
In the case of natural binary code:
In the case of Gray code, no such
problem occurs.

ASCII: American Standard Code for information interchange

Parity
Extra bits are added to aid in error detection and correction
Decimal Binary Even
parity
Odd parity
0 000 0000 0001
1 001 0011 0010
2 010 0101 0100
3 011 0110 0111
4 100 1001 1000
5 101 1010 1011
6 110 1100 1101
7 111 1111 1110
A 1-bit error changes the parity and thus can be detected

Multiplexers
I0
I1
S
2:1
mux
y
S
1
0
y
I0
I1
Y0
S
I0
I1
0
1
0
I0
0
I0

I0
S1
I1
I2
I3
S0
y
00
01 4:1
mux
10
11
y
I0
S1 S0
0 0
1
0
0
1
1 1
I1
I3
I2
S1
S0
I1
I0
I2
I3
Y

Mux is often used when resources have to be shared
8-bit ader
S1
a(0:7) b(0:7) c(0:7) d(0:7)
0 0 1
1
S2
Y
S1 S0
0 0
1
0
0
1
1 1
a+c
a+d
b+c
b+d
y =
0 0
a c
= a+c

Implementing Boolean expressions using Multiplexers
y
0
1
1 2 1 2
y x x x x
= +
1
x
?
?
x1 x2 y
0 0 0
0 1 1
y = x2 when x1 = 0
x2
1 0 1
1 1 0
y = x2 when x1 = 1
x2

( , , ) (1,2,6,7)
F x y z = 
A 3 variable function can be implemented with a 4:1 mux with 2 select lines
00
01
10
11
F
y z
F
x y z
0 0
0 0
0 0
1 0
F = 0 when yz = 00
0
0 1
0 1
0 1
1 0
F = x when yz =01
x
1 0
1 0
0 1
1 1
F = 1 when yz = 10
1
1 1
1 1
0 0
1 1
F = x when yz = 11
x
Mux is more efficient way of implementing combinational circuits as
compared to decoders. Internshala Trainings

Mux. expansion
1
0
E
S
y
I0
I1
y
S
E
I1
I0
0
0
0 x
1
1
1
E
0
1
E
0
1
I0
I1
I2
I3
S0 S0
S1
y
y
I0
S1 S0
0 0
1
0
0
1
1 1
I1
I3
I2
0
1 0
0
1
I1
I1

Mux. expansion
1
0
E
S
y
I0
I1
y
S
E
I1
I0
0
0
0 x
1
1
1
E
0
1
E
0
1
I0
I1
I2
I3
S0 S0
S1
y
y
I0
S1 S0
0 0
1
0
0
1
1 1
I1
I3
I2
1
0 1
0
1
I3
I3

DeMultiplexer
u-1
u-2
u-3
u-4
u-11
u-22
u-33
u-44
u-1
u-2
u-3
u-4
Mux
u-11
u-44
u-33
u-22
Demux
0
S0
1
2
3
S1
Data x
S1 S0
0 0
1
0
1
1 1
y0 y1 y2 y3
0
0 0 0
0
0 0
0 0 0
0
0
0
x
x
x
x

Demultiplexer is very much like a decoder
S0
S1
Data
3
2
1
0
Dmux
B
A
y2
y3
y1
y0
E
2/4
Y0 Y1 Y2 Y3
A
B
E
0
0
0
1
1 0 1 0 0
0 0 1 0
0 1
0
1
1
1
1
0
1
1
0
0
x x
1 0 0 0
0 0 0
0
B
A
E
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
Data
S0
S1
0
1
0
Data
1
0
0
0
S1 S0
0 0
1
0
1
1 1
y0 y1 y2 y3
0
0 0 0
0
0 0
0 0 0
0
0
0
x
x
x
x

Comparator
4-bit
comparator
A(0:3)
B(0:3)
A>B
A<B
A=B
A3A2A1A0 B3B2B1B0
0000
A<B A>B A=B
0000 0 1
0
0000 0001 1 0 0
0
0000
0001 1
0
a<b
a>b
a=b
a
b
1-bit
comparator
a
b
a
b
a=b
a
b a>b
a
b
a<b

1-bit
comparator
a3
b3
a3<b3
a3>b3
a3=b3
1-bit
comparator
a2>b2
a2=b2
a2
b2
a2<b2
1-bit
comparator
a1
b1
a1<b1
a1=b1
a1>b1
1-bit
comparator
a0
b0
a0<b0
a0>b0
a0=b0
A>B
A = B

Adder/Subtractor
a b S
0 0
0 0
0 0
1
0 1 1
0 0
1
0 1
1
0
1
1
1
1 1
0 0
0
1 1
0
0
1
1
0
1 0
0
0
1
1
1
1
Cin Cout
Half Adder
a b
S
C
a b S
0
0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
C
. . ; .
S a b a b C a b
= + =
a
b
C
S
a b
S
Full Adder
Cout Cin
1 1 0
1 1 1
1
1 1 1 1
. . . . . . . . ; . . .
in in in in out in in
S a b c a b c a b c a b c C a b a c b c
= + + + = + +

. . . . . . . .
in in in in
S a b c a b c a b c a b c
= + + +
. . .
out in in
C a b a C b C
= + +
( )
in
S C a b
=  
( . . ) . .( ) .
out in in
C C a b a b a b C a b a b
= + + =  +
a
b S
Cin
Cout
a b
 ( )
in
C a b
 
.
a b
.( )
in
C a b


4-bit Adder
A(0:3) B(0:3)
S(0:3)
Cout 4-bit adder
A3A2A1A0 B3B2B1B0
0000 1
0000 0001 0
0
0000
0001
S3S2S1S0 Cout
0000 0000
0001
0001
A3 A2 A1A0
B3 B2 B1B0
S3 S2 S1S0
C4
C1
C2
C3
FA
A0 B0
0
S0
C1
FA
A1 B1
S1
C2
FA
A2 B2
S2
C3
FA
A3 B3
S3
C4
Ripple Carry Adder (20 gate circuit)

Subtraction
A - B = A + 2’s complement of B
A - B = A + 1’s complement of B+1
FA
FA
FA
FA
A3 A2 A1 A0
1
B0
B1
B2
1
B3
A - B = A + B+1
0
B
1
B
2
B
3
B
One needs add a circuit for predicting errors resulting from overflow

Adder/Subtractor
FA
FA
FA
FA
A3 A2 A1 A0
B1 B0
B2
B3
0 FA
FA
FA
FA
A3 A2 A1 A0
1
B0
B1
B2
1
B3
FA
FA
FA
FA
A3 A2 A1 A0
B0
B1
B2
B3
M = 1

Multiplier B1 B0
A1 A0
A0B1 A0B0
A1B1 A1B0
multiplicand
multiplier
Partial products
C3 C2 C1 C0
HA
C0
C1
C2
A1
A0
B0
B0
B1
B1
HA
C3

SEQUENTIAL CIRCUITS

Digital Circuits
Combinational Circuits Sequential Circuits
CC
X
Y
W
Output is determined by current
values of inputs only.
CC
Storage
elements
X Z
Output is determined in general
by current values of inputs and
past values of inputs/outputs as
well.

NOR SR Latch
Q
Q
R
S
1; 0 Set State
Q Q
= =
0; 1 Re et State
Q Q s
= =
1
0
0
0
1
1 0 1 0
S R Q Q State
SET

NOR SR Latch
Q
Q
R
S
1; 0 Set State
Q Q
= =
0; 1 Re et State
Q Q s
= =
1
0
0
0 1
1 0 1 0
S R Q Q State
SET
0 1 0 1 RESET
Reset
Set

Q
Q
R
S
HOLD State
0
0
S R Q Q State
1 0 1 0 SET
0 1 0 1 RESET
0 0 HOLD
1
1
0
Q Q
1 1 0 0 INVALID

Q
Q
R
S
1
1
0
0
Both the outputs are well defined and
0. the first problem is that we do not
get complementary output.
A more serious problem occurs when we switch the latch to the hold state by
changing RS from 11 → 00 . Suppose the inputs do not change
simultaneously and we get the situation 11 → 01* → 00
Q
Q
R
S
Q
Q
R
S
Q
Q
R
S
1
1
0
0
0
1
1
0
0
0
1
0
Q = 1

Q
Q
R
S
Q
Q
R
S Q
Q
R
S
1
1
0
0
0
1
1
0
0
0
1
0
Q = 1
Q
Q
R
S
Q
Q
R
S
Q
Q
R
S
1
1
0
0
1
0
0
1
0
0
0
1
Q = 0
Suppose the inputs change as RS = 11 → 10* → 00
So although output is well defined when we apply RS = 11, it becomes
unpredictable once we switch the latch to hold state by applying RS = 00. That
is why RS = 11 is not used as an input combination.

The error can occur also due to unequal gate delays.
Q
Q
R
S
1
2
1
1
0
0
Q
Q
R
S
1
2
0
0
0
0
Suppose gate-1 is faster
Q
Q
R
S
1
2
0
0
1
0
0
Q = 1
On the other hand suppose that gate-2 is faster.
Q
Q
R
S
1
2
1
1
0
0
Q
Q
R
S
1
2
0
0
0
0 Q
Q
R
S
1
2
0
0
1
0
0
Q = 0
Again the output is unpredictable in general

NAND Latch
Q
Q
R
S
S R Q Q State
0 1 1 0 SET
1 0 0 1 RESET
1 1 HOLD
Q Q
0 0 1 1 INVALID

RS NAND Latch with Enable
Q
Q
R
S
EN
0
1
1
Hold State
Q
Q
R
S
EN
1
S
R
Enable State
S R Q Q
0
1
1
1
1
Hold
Set
Reset
Hold
Invalid
x x
1 0 1 0
0 1 0 1
Q Q
Q Q
1 1
0 0
0 0

D latch
Q
Q
S
R
Q
S
R Q
D
EN
EN
Enable State
S R Q Q
0
1
1
1
1
Hold
Set
Reset
Hold
Invalid
x x
1 0 1 0
0 1 0 1
Q Q
Q Q
1 1
0 0
0 0
1 1
0
0
1
If EN = 1 then Q = D otherwise the latch is in Hold state
1
Q
Q
D
EN

CC
Storage
elements
X Z
Synchronous Sequential Circuits
Clock
Data (x)
Data is stable when clock is high
n
X(n)

an
bn
cn
Q
D
clk
zn
yn
Clock
an
bn
cn
Example
y
0
1
0
0
0 0
1
0
z

an
bn
cn
Q
D
clk
zn
yn
Clock
an
bn
cn
Example
y
1
1
1
0
0 1
1
1
z
1
1
0
0

Problem with Latch
Q
D
clk
zn
yn
1
1
clk
y
Circuits are designed with the idea there
would be single change in output or
memory state in single clock cycle.
z

Edge Triggered Latch or Flip-flop
Q
D
clk
Clock
D
Positive edge triggered flipflop

Negative Edge Triggered Latch or Flip-flop
Q
D
clk
Clock
D

Master-Slave D Flip-flop
EN
Q
Q
D
EN
D
D
clk
slave
master
Clock
D
Master
Slave
Q
D
clk

Q
1
2
3
4
5
6
Q
S
R
D
clk
Positive edge triggered Flip-flop
0
1
1
0
1
1
1
0
→1
→0 →1
→0

Q
1
2
3
4
5
6
Q
S
R
D
clk
Positive edge triggered Flip-flop
1
0
1
1
0
1
1
0
→0 →1
A change in input has no effect if it occurs after the clock edge

1
3
D
clk
Q
5 Q
S
6
4
2
R
Reset
Positive edge Triggered Flip-flop with Asynchronous Reset
0
1
1
0
Q
D
clk
R

Characteristic table
Q
D
clk
Q(t+1)
Inputs (D)
0 0
1 1
Q
clk
J
K
Q(t+1)
Inputs
JK Flip-flop
J K
0 0 Q(t)
0
0 1
1 0 1
1 1 Q(t)
Given a input and the present state of the flip-flop,
what is the next state of the flip-flop
( 1)
Q t D
+ =
( 1) ( ). ( ).
Q t Q t J Q t K
+ = + →Characteristic equation

Q
clk
T Q(t+1)
Inputs (T)
0 Q(t)
1
Toggle or T Flip-flop
Q(t)
Excitation Table
Inputs
0 0
0 1
1 0
1 1
Q(t+1)
Q(t) T
What inputs are required to effect a particular state change
0
0
1
1
( 1) ( ). ( ).
Q t Q t T Q t T
+ = +

Excitation Table
Q
clk
J
K
J K Q(t+1)
Q(t)
0 0
0 1
1 0
1 1 Q(t)
0
1
Inputs
0 0
0 1
1 0
1 1
Q(t+1)
Q(t)
X 0
J K
0 X
1 X
X 1
Q
D
clk
Q(t+1)
D
0 0
1 1
Inputs
0 0
0 1
1 0
1 1
Q(t+1)
Q(t) D
0
1
0
1

Convert a D FF to JK FF
clk
Q
D
K
CC
J
J K Q(t+1)
0 0
0 1
1 0
1 1 Q(t)
0
1
Q(t)
D
Q(t)
0
1
Q(t)
00 01 11
0
1
10
0 0
1
Q
JK
1
0
1
1
0
. .
D Q J Q K
= +
clk
D
K
J
Q
Q

Digital_Electronics_Basics.pdf

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