This document defines a RAM entity with an 8-bit address port, 8-bit bidirectional data port, and write enable, chip select, and output enable control ports. The architecture implements the RAM using a 256x8 RAM array. It uses a process sensitive to the control signals and address to either write data to or read data from the RAM location selected by the address value.

1. library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity ram is
port (address: in std_logic_vector(7 downto 0);
data: inout std_logic_vector(7 downto 0);
WE, CS, OE: in std_logic);
end entity ram;
architecture simple_ram of ram is
type ram_type is array (0 to 255) of std_logic_vector(7 downto 0);
signal ram1: ram_type:= (others => (others => '0'));
begin
process(WE,CS,OE,address)
begin
data <= (others => 'Z');
if (CS = '0') then
if WE='1' and OE = '1' then
ram1(conv_integer(address)) <= data;
end if;
if WE = '0' and OE = '0' and CS = '0' then
data <= ram1(conv_integer(address));
END IF;
else
data <= (others => 'Z');
-- end if;
end if;
end process;
end simple_ram;