1. PRIYANKA AGGARWAL
Contact No: 08860711309, 09213280699
Email Id: priyanka.sarika1992@gmail.com
Current Location: Gurgaon
CURRENT OBJECTIVE
Seeking a challenging position as an Intern for six months duration from Jan to Jun, 2016 to learn
further in VLSI Domain (RTL Design & Verification), in your company.
CAREER OBJECTIVE
Seeking a challenging position as an employee to utilize my skills and abilities for the welfare of a VLSI
Domain (RTL Design & Verification) company that offers professional growth while being resourceful
and innovative.
SCHOLASTICS
M. Tech (VLSI Design) from NCU(Formerly ITMU), Gurgaon, Haryana
with 7.8 CGPA 2014-present
B. Tech (ECE) from, Maharishi Dayanand University, Haryana with 79.5% 2012-2014
10+2 from CBSE, New Delhi in year 2008 with 86.6% 2009-2010
10th from CBSE, New Delhi in year 2008 with 74.8% 2007-2008
TOOLS
HDL Simulators : NCSIM (from Cadence Design Systems)
FPGA Prototyping : Xilinx ISE 14.5, Xilinx Spartan 3AN
Circuit Simulators : Cadence Virtuoso
Operating Systems : Windows, Linux.
RTL Verification : Questasim_10.0b( from Mentor Graphics)
MOS devices : Atlas, Silvaco (TCAD Tool)
HARDWARE AND SOFTWARE LANGUAGES
Hardware Programming Languages : Verilog, VHDL
Software Programming Languages : C++, C
Scripting Language : Shell Scripting, Tcl/Tk
Verification language : SystemVerilog
PROJECTS
SystemVerilog projects : Verified a Design of a no.of 1’s-Counter, I2C Protocol, SPI Protocol by
Creating Verification Environment using SystemVerilog
RTL to GDSII Flow : For FIFO using tools provided by Cadence:
Incisive Unified Simulator 9.2/10.2
RTL Compiler 10.1
Encounter Digital Implementation 9.1/11.1
FPGA Implementation : Implemented conventional digital multiplier of 2-bit and 4-bit
Verilog HDL Project : Did project on ‘Traffic Light Controller’
2. REVIEW WORK
Study on Different kinds of multipliers : Did review on different kinds of multiplier,
Studied the FSM approach for implementing
Pipelined Multiplier using Verilog HDL
WORKSHOP
Hands-on Vivado Design Tool Flow using ZED Board : held on 27th
Feb,2015 at Guru Tegh
Bahadur College, Delhi
INTERNSHIP
Underwent 1.5 months of SystemVerilog training from Xinoe system, Gurgaon
STRENGTHS
Good communication, analytical and problem solving skills.
Dedicated and highly ambitious to achieve personal as well as organizational goals.
Learning agility and adaptable.
Positive Attitude.
Firm believer of “Not beating the Deadline is Not meeting the Deadline”.
PERSONAL VITAE
Date of Birth : 16-06-1992
Hobbies : Listening to Music, Singing
Father’s Name : Mr. Mahesh Aggarwal
Mother’s Name : Mrs. Rajni Aggarwal
Linguistic Proficiency : Hindi, English, German
Address : 741/171,Street No-3A,Shivaji Nagar,Khandsa Road , Gurgaon
REFERENCE
Dr. Neeraj Kr. Shukla Associate Professor & Project Manager
Department of EECE
North Cap University
HUDA Sector-23A,
Gurgaon-122017 (Haryana) India
E-Mail: neerajkshukla@ncuindia.edu
Contact No. +91-9212628151
Dr. Swaran Ahuja HOD & Dean Professor
Department of EECE
North Cap University
HUDA Sector-23A,
Gurgaon-122017 (Haryana) India
E-Mail: swaranahuja@ncuindia.edu
DECLARATION
I hereby affirm that the information furnished above is true and correct, to the best of my knowledge.
Place: Gurgaon
