2. Introduction
⢠Load store architecture
⢠Uses basic RISC with certain enhancements:
-Barrel shifter
-Increment/decrement operations without
ALU
3. Data Sizes and Instruction Sets
⢠The ARM is a 32-bit architecture.
⢠When used in relation to the ARM:
â Byte means 8 bits
â Halfword means 16 bits (two bytes)
â Word means 32 bits (four bytes)
⢠Most ARMâs implement two instruction sets
â 32-bit ARM Instruction Set
â 16-bit Thumb Instruction Set
4. Processor Modes
⢠The ARM has seven basic operating modes:
â User : unprivileged mode under which most tasks run
â FIQ : entered when a high priority (fast) interrupt is raised
â IRQ : entered when a low priority (normal) interrupt is raised
â Supervisor : entered on reset and when a Software Interrupt
instruction is executed
â Abort : used to handle memory access violations
â Undef : used to handle undefined instructions
â System : privileged mode using the same registers as user mode
6. ARM Register Set
ARM has 37 registers all of which are 32-bits long.
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
The current processor mode governs which of several banks is accessible. Each mode
can access
a particular set of r0-r12 registers
a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
the program counter, r15 (pc)
the current program status register, cpsr
Privileged modes (except System) can also access
a particular spsr (saved program status register)
7. Program Status Registers
⢠Condition code flags
â N = Negative result from ALU
â Z = Zero result from ALU
â C = ALU operation Carried out
â V = ALU operation oVerflowed
⢠Sticky Overflow flag - Q flag
â Architecture 5TE/J only
â Indicates if saturation has occurred
⢠J bit
â Architecture 5TEJ only
â J = 1: Processor in Jazelle state
⢠Interrupt Disable bits.
â I = 1: Disables the IRQ.
â F = 1: Disables the FIQ.
⢠T Bit
â Architecture xT only
â T = 0: Processor in ARM state
â T = 1: Processor in Thumb state
⢠Mode bits
â Specify the processor mode
2731
N Z C V Q
28 67
I F T mode
1623 815 5 4 024
f s x c
U n d e f i n e dJ
8. Program Status Registers
⢠Condition code flags
â N = Negative result from ALU
â Z = Zero result from ALU
â C = ALU operation Carried out
â V = ALU operation oVerflowed
⢠Sticky Overflow flag - Q flag
â Architecture 5TE/J only
â Indicates if saturation has occurred
⢠J bit
â Architecture 5TEJ only
â J = 1: Processor in Jazelle state
⢠Interrupt Disable bits.
â I = 1: Disables the IRQ.
â F = 1: Disables the FIQ.
⢠T Bit
â Architecture xT only
â T = 0: Processor in ARM state
â T = 1: Processor in Thumb state
⢠Mode bits
â Specify the processor mode
2731
N Z C V Q
28 67
I F T mode
1623 815 5 4 024
f s x c
U n d e f i n e dJ