This ppt will help you to do complet study of Sci fuctional block diagram and full details about register used in sci . one sample uart transmit code logic explained briefly.

1. Chapter 8 : Serial
Communication Interface
C28x
Digital Signal Controller
TMS320F2812
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2. SCI Pin Connections
TX FIFO_0 (Full Duplex Shown) TX FIFO_0
TX FIFO_15 TX FIFO_15
Transmitter-data Transmitter-data
buffer register buffer register
8 8
Transmitter SCITXD SCITXD Transmitter
shift register shift register
Receiver SCIRXD SCIRXD Receiver
shift register shift register
8 8
Receiver-data Receiver-data
buffer register buffer register
RX FIFO_0 RX FIFO_0
RX FIFO_15 RX FIFO_15
TechnologySCI Device #1
beyond the Dreams™ SCI Device #2
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3. SCI-A Programmable Data Format
NRZ (nonreturn to zero) format
Addr/
Start LSB 2 3 4 5 6 7 MSB Parity Stop 1 Stop 2
Data
This bit present only in Address-bit mode
Majority
Vote
SCICLK
(Internal)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2
SCIRXD
Start Bit LSB of Data
Falling Edge Detected Note: 8 SCICLK periods per data bit
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4. Multiprocessor Wake-Up Modes
• Allows numerous processors to be hooked up to the bus, but transmission
occurs between only two of them
• Idle-line or Address-bit modes
• Sequence of Operation
1. Potential receivers set SLEEP = 1, which disables RXINT except when an
address frame is received
2. All transmissions begin with an address frame
3. Incoming address frame temporarily wakes up all SCIs on bus
4. CPUs compare incoming SCI address to their SCI address
5. Process following data frames only if address matches
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5. Idle-Line Wake-Up Mode
• Idle time separates blocks of frames
• Receiver wakes up with falling edge after SCIRXD was high for 10 or more
bit periods
• Two transmit address methods
– deliberate software delay of 10 or more bits
– set TXWAKE bit to automatically leave exactly 11 idle bits
Idle periods
of less than Block of Frames
10 bits
SCIRXD/ Last Data SP ST Addr SP ST Data SP ST Last Data SP ST Addr SP
SCITXD
Idle Address frame 1st data frame Idle
Period follows 10 bit Period
10 bits 10 bits
or greater or greater idle or greater
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6. Address-Bit Wake-Up Mode
• All frames contain an extra address bit
• Receiver wakes up when address bit detected
• Automatic setting of Addr/Data bit in frame by setting TXWAKE = 1
prior to writing address to SCITXBUF
Block of Frames
SCIRXD/ Last Data 0 SP ST Addr 1 SP ST Data 0 SP ST Last Data 0 SP ST Addr 1 SP
SCITXD
First frame within 1st data frame
no additional
Idle Period block is Address. idle bits needed
length of no ADDR/DATA beyond stop bits
significance bit set to 1
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7. SCI Summary
• Asynchronous communications format
• 65,000+ different programmable baud rates
• Two wake-up multiprocessor modes
– Idle-line wake-up & Address-bit wake-up
• Programmable data word format
– 1 to 8 bit data word length
– 1 or 2 stop bits
– even/odd/no parity
• Error Detection Flags
– Parity error; Framing error; Overrun error; Break detection
• FIFO-buffered transmit and receive
• Individual interrupts for transmit and receive
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8. SCI-A Registers
Address Register Name
0x007050 SCICCR SCI-A commun. control register
0x007051 SCICTL1 SCI-A control register 1
0x007052 SCIHBAUD SCI-A baud register, high byte
0x007053 SCILBAUD SCI-A baud register, low byte
0x007054 SCICTL2 SCI-A control register 2 register
0x007055 SCIRXST SCI-A receive status register
0x007056 SCIRXEMU SCI-A receive emulation databuffer
0x007057 SCIRXBUF SCI-A receive data buffer register
0x007059 SCITXBUF SCI-A transmit data buffer register
0x00705A SCIFFTX SCI-A FIFO transmit register
0x00705B SCIFFRX SCI-A FIFO receive register
0x00705C SCIFFCT SCI-A FIFO control register
0x00705F SCIPRI SCI-A priority control register
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9. SCI-A Communication Control Register
Communications Control Register (SCICCR) – 0x007050
7 6 5 4 3 2 1 0
STOP EVEN/ODD PARITY LOOP BACK ADDR/IDLE SCI SCI SCI
BITS PARITY ENABLE ENABLE MODE CHAR2 CHAR1 CHAR0
0 = 1 Stop bit 0 = Disabled 0 = Idle-line mode # of data bits = (binary + 1)
1 = 2 Stop bits 1 = Enabled 1 = Addr-bit mode e.g. 110b gives 7 data bits
0 = Odd 0 = Disabled
1 = Even 1 = Enabled
Technology beyond the Dreams™ Control Register (SCICCR) – 0x007750]
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10. SCI-A Control Register 1
Control Register 1 (SCICTL1) – 0x007051
7 6 5 4 3 2 1 0
reserved RX ERR SW reserved TXWAKE SLEEP TXENA RXENA
INT ENA RESET
0 = receiver disabled
1 = receiver enabled
0 = transmitter disabled
1 = transmitter enabled
0 = sleep mode disabled
1 = sleep mode enabled
Transmitter wakeup method select
1 = wakeup mode depends on SCICCR.3
0 = no wakeup mode
Write 0 = Reset SCI
Write 1 = release from Reset
0 = Receive Error Interrupt disabled
1 = Receive Error Interrupt enabled
Technology beyond the Dreams™ 0x007751]
[SCI-B Control Register 1 (SCICTL1) – Copyright © 2006 Pantech Solutions Pvt

11. 16
SCI-A Baud Rate
BRR = 0 ,
LSPCLK
SCI baud rate =
(BRR + 1) x 8
BRR = 1 to 65535 ,
LSPCLK
Baud-Select MSbyte Register (SCIHBAUD) – 0x007052
7 6 5 4 3 2 1 0
BAUD15 BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8
(MSB)
Baud-Select LSbyte Register (SCILBAUD) – 0x007053
7 6 5 4 3 2 1 0
BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD0
(LSB)
[SCI-B Baud-Select MSbyte Register (SCIHBAUD) – 0x007752]
[SCI-B Baud-Select LSbyte Register (SCILBAUD) – 0x007753]
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12. SCI-A Control Register 2
SCICTL2 @ 0x007054
15 - 8 7 6 5-2 1 0
reserved TX reserved RX/BK TX
TXRDY
EMPTY INT ENA INT ENA
SCI RX/BK INT ENA
0 = Disable RXRDY/BRKDT interrupt
1 = Enable RXRDY/BRKDT interrupt
SCI TX EMPTY
0 = TXBUF or shift register are loaded with data
1 = Transmit buffer and shift register both empty
SCI TX READY
SCI TX INT ENA
0 = SCITXBUF is full
0 = Disable TXRDY interrupt
1 = SCITXBUF is empty
1 = Enable TXRDY interrupt
Technology beyond the Dreams™ 0x007754]
[SCI-B Control Register 2(SCICTL2) – Copyright © 2006 Pantech Solutions Pvt

13. SCI-A Receiver Status Register
SCIRXST @ 0x007055
7 6 5 4 3 2 1 0
RX RXRDY BRKDT FE OE PE RXWAKE reserved
ERROR
1 = Receiver wakeup
condition detected
1 = Parity Error detected
1 = Overrun Error detected
1 = Framing Error detected
1 = Break condition occurred
0 = no break condition
0 = no new character in SCIRXBUF
1 = new character in SCIRXBUF
0 = No error flags set
1 = Error flag(s) set
[SCI-B Receiver Status Register (SCIRXST) – 0x007755]
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14. SCI-A FIFO Transmit Register
SCIFFTX @ 0x00705A
SCI FIFO TX FIFO Status (read-only)
Enhancements 00000 TX FIFO empty
0 = disable TX FIFO Reset
00001 TX FIFO has 1 word
1 = enable 0 = reset (pointer to 0)
00010 TX FIFO has 2 words
1 = enable operation00011 . TX FIFO.has 3 words.
SCI Reset .
. .
. .
.
0 = reset 10000 TX FIFO has 16 words
1 = enable operation
15 14 13 12 11 10 9 8
TXFIFO
SCIRST SCIFFENA TXFFST4 TXFFST3 TXFFST2 TXFFST1 TXFFST0
RESET
7 6 5 4 3 2 1 0
TXFFINT
TXFFINT TXFFIENA TXFFIL4 TXFFIL3 TXFFIL2 TXFFIL1 TXFFIL0
CLR
TX FIFO TX FIFO TX FIFO TX FIFO Interrupt Level
Interrupt Interrupt Interrupt
Flag (read-only) Flag Clear (on match) Interrupt when TXFFST4-0
0 = not occurred 0 = no effect Enable and TXFFIL4-0 match
1 = occurred 1 = clear 0 = disable
1 = enable
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15. SCI-A FIFO Receive Register
SCIFFRX @ 0x00705B RX FIFO Status (read-only)
RX FIFO RX FIFO 00000 RX FIFO empty
Overflow Overflow RX FIFO Reset00001 RX FIFO has 1 word
Flag (read-only) Flag Clear 0 = reset (pointer to00010
0) RX FIFO has 2 words
0 = no overflow 0 = no effect 1 = enable operation 00011 . RX FIFO.has 3 words.
1 = overflow 1 = clear .
. .
. .
.
10000 RX FIFO has 16 words
15 14 13 12 11 10 9 8
RXFF- RXFF- RXFIFO
RXFFST4 RXFFST3 RXFFST2 RXFFST1 RXFFST0
OVF OVF CLR RESET
7 6 5 4 3 2 1 0
RXFFINT
RXFFINT RXFFIEN RXFFIL4 RXFFIL3 RXFFIL2 RXFFIL1 RXFFIL0
CLR
RX FIFO RX FIFO RX FIFO RX FIFO Interrupt Level
Interrupt Interrupt Interrupt
Flag (read-only) Flag Clear (on match) Interrupt when RXFFST4-0
0 = not occurred 0 = no effect Enable and RXFFIL4-0 match
1 = occurred 1 = clear 0 = disable
1 = enable
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16. SCI-A FIFO Control Register
SCIFFCT @ 0x00705C
Auto Baud Auto Baud
detection detection CDC calibrate ‘A’
Flag (read-only) Flag Clear 0 = disabled auto-baud alignment
0 = not complete 0 = no effect 1 = enables auto-baud alignment
1 = complete 1 = clear
15 14 13 12 11 10 9 8
ABD
ABD CDC reserved
CLR
7 6 5 4 3 2 1 0
FFTXDLY
Time delay between every transfer from FIFO
to transmit shift register
in number of SCI baud clock cycles
( 0 to 255 )
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17. SCI Example 1: transmit a text - string
 Lab 8: Basic SCI Communication
 Send a string from DSP to a PC’s COM-port.
 Connect the RS232 - Connector of the board with a standard DB9 - cable
( 1:1 ) to a serial port of the PC (COM1or COM2).
 DSP shall transmit a string from the DSP to the PC periodically.
 No SCI interrupt services in this lab
 After transmission of the first character we just poll the transmission ready
flag (TXEMPTY) before loading the next character into the transmit buffer -
and wait again.
 The Windows-Hyper Terminal program is used as the counterpart from the
PC’s-side and must be initialized properly for correct function(Baud rate,
Parity, no protocol).
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