Slides from my talk on Programmable Logic at the Open Source Hardware Users Group Meeting #9 in London on the 21st of April 2011. More details about the event at: http://oshug.org/event/9 An overview of the slides at: http://omer.me/2011/05/a-quick-introduction-to-programmable-logic

1. AQuick Introduction toProgrammable Logic.Omer Kilic – OSHUG #9, April 2011

2. http://omer.kilic.name

3. Agenda History of Digital Electronics Programmable Logic Devices Design ‘flow’ for FPGAs State of the Art / Challenges Q & A

4. 1854 AND NOT OR George Boole Inventor of Boolean Logic An Investigation of the Laws of Thought http://www.gutenberg.org/ebooks/15114

5. Logic Functions

6. 1937 Claude Shannon Designs first electrical application utilising Boolean Theory A Symbolic Analysis of Relay and Switching Circuits http://dspace.mit.edu/handle/1721.1/11173

7. 1947: Point-contact transistor invented at Bell Labs 1954: Texas Instruments introduces first commercial silicon transistor

8. http://www.flickr.com/photos/andy_squirrel/4701062117

9. Logic Families

10. 7400 Series (TTL)

12. http://www.flickr.com/photos/dnny/1435262760/

14. Application-Specific Integrated Circuit

15. Programmable Logic Array

16. Programmable Array Logic

17. Complex Programmable Logic Device ‘Macrocells’ EEPROM/Flash Non-volatile configuration Instant-on Not-OTP! Coarse Grain

18. Field Programmable Gate Array ‘Field Programmable’ Based on blocks of logic and a flexible interconnect matrix Fine Grain Used in: digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation, radio astronomy, metal detection,…

19. Programmable Logic Vendors

24. Configurable Logic Block

25. Configurable Logic Block Slice Slice Slice Slice

26. Configurable Logic Block Slice Slice Logic Cell Logic Cell Logic Cell Logic Cell Slice Slice Logic Cell Logic Cell Logic Cell Logic Cell

29. Aside: Software Compilation main.s .file "main.c" .section .rodata .LC0: .string "hello, world" .text .globl main .type main, @function main: leal 4(%esp), %ecx andl $-16, %esp pushl -4(%ecx) pushl %ebp movl %esp, %ebp pushl %ecx subl $4, %esp movl $.LC0, (%esp) call puts movl $0, %eax addl $4, %esp popl %ecx popl %ebp leal -4(%ecx), %esp ret .size main, .-main .section .note.GNU-stack,"",@progbits main.c #include <stdio.h> int main(void) { printf("hello, world"); return 0; } gcc -S main.c http://en.wikipedia.org/wiki/X86_instruction_listings

30. FPGA Design Flow Behavioural Simulation Post-Synthesis Simulation Post-PAR Simulation

31. Design Entry Schematic Based Hardware Description Languages VHDL Verilog Constraints definition ‘Floorplan’ Timing Power “Which HDL do you prefer?” “The one I'm not using this week” Janick Bergeron

32. VHDL vs Verilog Example: 8-bit shift-left register with a positive-edge clock, serial in, and serial out VHDL library ieee;use ieee.std_logic_1164.all;entity shift is port(C, SI : in std_logic; SO : out std_logic);end shift; architecture Behav of shift is signal tmp: std_logic_vector(7 downto 0);beginprocess (C)begin if (C'event and C='1') then for i in 0 to 6 looptmp(i+1) = tmp(i); end loop; tmp(0) = SI; end if;end process; SO = tmp(7);end Behav; Verilog module shift (C, SI, SO); input C,SI;output SO;reg [7:0] tmp; always @(posedge C) begintmp= tmp<< 1;tmp[0] = SI; end assign SO = tmp[7];endmodule From: http://www.xilinx.com/itp/3_1i/data/fise/xst/chap02/xst02007.htm

33. VHDL vs Verilog “Verilog was written by a bunch of hardware guys who knew nothing about software. We beat on it 'till you could do software with it.” “VHDL was written by a bunch of software guys who knew nothing about hardware. We beat on it 'till you could do hardware with it.” http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4

34. Synthesis Check Syntax Analyse/Optimise hierarchy of design Translate Schematic/HDL code into a ‘netlist’

35. Implementation Translate Merges netlists/constraints (Functional Simulation) Map Maps design onto physical FPGA blocks (CLB, IOB, etc.) (Static Timing Analysis) Place & Route (PAR) Places ‘mapped’ blocks onto FPGA fabric and arranges connections between them (Static Timing Analysis) Produces ‘bitstream’

36. Programming Most FPGAs are SRAM based Volatile configuration External configuration memory JTAG

37. Simulation!

38. FPGA Design Flow Behavioural Simulation Post-Synthesis Simulation Post-PAR Simulation

39. Xilinx Microblaze ‘Softcore’ Processor

40. Xilinx Microblaze ‘Softcore’ Processor

41. Xilinx ML605 http://bit.ly/xilinx-ml605

42. Avnet Spartan-6 LX9 MicroBoard http://bit.ly/avnet-s6-microboard Digilent Basys2 http://bit.ly/digilent-basys2

43. Enterpoint Merrick1 100+1 FPGAs 10 x 10 array of Spartan™-3A DSP XC3SD3400A and a Virtex™-5 XC5VLX30T “A standard Merrick1 can be rented at GBP £2000, USD $3000, per month subject to minimum rental period and deposit. Additional costs for shipping, insurance and taxes may also apply.” http://bit.ly/enterpoint-merrick1

44. State of the Art

45. State of the Art

46. State of the Art

47. Challenges Toolchains are complicated, costly and (mostly) closed source Lack of standardised frameworks or workflows Advances in device capabilities not fully utilised by applications

48. Thanks! Any Questions?