It includes 486DX Architecture with Register Organization

1. 486 or 80486DX Architecture

2. Functional units of 80486
• BIU (Bus Interface Unit)
• Code prefetch unit
• Instruction decoding unit
• Control & protection test unit
• Execution unit
• Floating Point Unit (FPU)
• Segmentation unit
• Paging unit
• Cache unit
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3. Block diagram of 80486
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4. Continued
• The execution unit executes a series of micro instruction.
• The barrel shifter is a special type of shift register performs
multiple number of shifts in a single operation.
• MMU contains segmentation and paging. The segmentation unit
computes physical address from logical address.
• The paging unit converts linear address to physical address also
logical address to physical address conversion is required.
• The paging unit has TLB (Translation Lookaside Buffer) – It keeps
a cache (static RAM) of most recently accessed pages.
• There is a control ROM with the control and protection test
unit.
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5. Continued
• The 80486 has a built in math co-processor (FPU). It executes
trigonometric, logarithmic, exponential and arithmetic
instructions.
• The cache unit consists of an 8KB code and data.
• The BIU interfaces with memory and I/O devices to 486
microprocessor. The code prefetch unit fetches the instruction
in the queue. The instruction decoding unit receives the
instruction codes from prefetch unit and decodes them. Then
Execution unit executes them.
• Protection is very essential for multiuser system. It helps to
isolate operating system to user task and user tasks from each
other.
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6. Elements of BIU
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7. Continued…
• The address drivers are used to drive the address out onto the
processor's local address bus (A31:A2), and control logic for
signaling whether a memory I/O, or interrupt acknowledgement
bus cycle is to be performed.
• Data bus transceivers – It is used to get the data onto the
processor's local data bus during read / write bus cycles
• Write buffers – It allow the bus unit to buffer to permit write
operations to complete the execution instantly.
• Bus size control logic – It senses when the microprocessor is
communicating with 8 or 16 bit devices, causing the
microprocessor to automatically execute multiple bus cycles
when necessary.
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8. Continued…
• Bus control request sequencer – It determines the order of
addressing during burst transfers.
• Burst bus control logic – It is used to control the buses during
the execution of a burst transfer.
• Cache control logic – It connects the processor's local buses to
the external cache controller.
• Parity generation / checking logic – The parity is used to check
whether the data are read correctly from the memory. It
generates an error signal if there is an error.
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9. For Understanding purpose
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10. Register Organization of 486
Microprocessor
• It contains 8, 32-bit general purpose registers they are shown in
the below figure.
The Prefix in EAX, EBX, ECX etc., stands for “Extended”.
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11. Segment registers
• The 486 contains 6, 16-bit segment registers.
• FS & GS are the two additional data segment registers.
• [Total Virtual Memory Space: 4GB * 16 K = 64 TB]
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12. Instruction Pointer & Flag Registers
• The Extended Instruction Pointer holds the offset of next
instruction to be executed.
• EIP is always relative to the starting address of the code
segment contained by CS.
• EFLAGS contains 14 flags out of 14, 6 are conditional flags and
remaining flags are control & system flags.
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13. CFVM RF 0 NT IOPL OF IF TF SF ZF 0 AF 0 PF 1
0123456789101112131415
DF
16171831
RESERVED FOR
INTEL
E
F
L
A
G
FLAGS
AC
Status (conditional) flags
1. CF: Carry Flag
2. PF : Parity Flag
3. AF: Auxiliary carry
4. ZF: Zero Flag
5. SF : Sign Flag
6. OF : Over Flow
Control & System Flags
1. DF : Direct Flag
2. TF : Trap Flag
3. IF : Interrupt Flag
4. AC : Alignment Check
5. NT : Nested Task Flag
6. RF : Resume Flag
7. VM : Virtual Mode
8. IOPL : I/O Privilege Level Flag
Flag Register of 80486 Microprocessor
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14. Status (conditional) flags
Carry flag (CY)
It is set whenever there is a carry or borrow out of the MSB of a result.
CY=1, Carry is generated
CY=0, Carry is not generated
Parity flag (PF)
It is set(1) if the result has even parity. If parity is odd, PF is reset(0).
Auxiliary carry flag (AC)
Holds a carry after addition or a borrow after subtraction between bit
positions 3 and 4 of the result.
Zero flag (ZF)
Indicates that the result of an arithmetic or logic operation It is set if
the result is zero
Sign flag (SF)
Indicates the arithmetic sign of the result after an addition or
subtraction. If S = 1, the result is negative. If S = 0, the result is positive.

15. Overflow flag (OF)
A overflow condition indicates that a result has exceeded the capacity of
the machine. A condition that can occur when signed numbers are added
or subtracted.
Control & System Flags
Trap or Trace flag (TF)
Debugging feature of the microprocessor
Interrupt flag (IF) - interrupt controls operation
If I = 1, the INTR pin is enabled. If I = 0, the INTR pin is disabled.
Direction flag (DF)
Controls the selection of increment and decrement for the DI and SI
registers during string instructions.
Alignment Check, AC
If AC flag set to 1, it indicates misaligned memory address.
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16. Virtual 8086 Mode Flag (VM)
This flag provides 8086 mode operation within the protected mode of 486
microprocessor by setting the flag to 1.
Resume (or) Restart Flag, RF
When the resume flag is set to 1 a debug fault is ignored on the next
instruction.
Nested Task, NT
It indicates the execution of the current task is nested within another
task.
I/O Privilege Level Flag, IOPL
It indicates the maximum privilege level allowed for the execution of I/O
instructions.
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17. Special purpose registers
• Segment Descriptor Cache Registers
• System Level Registers
• FPU Registers
• Debug Registers
• Test Registers
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18. Segment Descriptor Cache Registers
• It is associated with each segment registers.
• The segment register is loaded with selector for memory
reference.
• The necessary information is read from the descriptor table.
• The information includes, 32 bit base address, 32 bit segment
limit etc.,
• Segment descriptor cache registers are invisible to programmer
whereas segment registers are visible to programmer.
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19. System Level Registers
• It provide to control the operation of the on-chip cache, FPU,
segmentation & paging mechanism.
• It contain 3 control registers & 4 system address registers.
• Control Registers: CR0 – CR3
• CR0: Control the co-processor, paging mechanism, on-chip cache etc.,
• CR2: 32 bit linear address that cause the last page fault detected.
• CR3: It holds the physical base address of the page directory table.
• CR1 is reserved for future microprocessor.
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20. Continued
• Linear Address, created by adding logical address to the
base of segment, CS, DS, ES, SS, FS, GS.
• When Paging is enabled, the page tables are used to
translate linear address to physical address.
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21. System address registers
• There are 4 s/y address registers as,
• GDTR – It contains the memory base address and length of the
global descriptor table.
• IDTR – It contains the memory base address and length of the
interrupt descriptor table.
• LDTR – It contains the memory base address and length of the
local descriptor table.
• TR – It describes the executing tasks.
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22. FPU Registers
• It contains 8 data registers, a tag word, a control register, a
status register, an instruction pointer & data pointer.
Debug Registers:
• It contains 6 debug registers as,
DR0 – DR3: hold four break points
DR7: sets the break points
DR6: debug status register (i.e., current state of the break
points)
DR4 & DR5: Reserved for use in future microprocessor.
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23. Test Registers
• It contains 5 test registers as,
• TR3 – TR7. In that, T3, T4 & T5 are used to test the on-chip cache.
• TR6 & TR7 control the testing of the Translation Lookaside Buffer
(TLB).
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24. THANK YOU
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