2. 1. ARITHMETIC LOGIC UNIT
ALU units typically
need to be able to
perform the basic
logical operations
(AND, OR) and the
addition operation.
The inclusion of
inverters on the inputs
enables the same ALU
hardware to perform the
subtraction operation
(adding an inverted
operand), and the
operations NAND and
NOR.
3. EXAMPLE OF ALU ( 2 BITS )
This is an example of a basic 2-bit ALU. The boxes on the right hand side of the
image are multiplexers and are used to select between various operations: OR,
AND, XOR, and addition.
5. 2. CONTROL UNIT
The Control Unit is one of the most important parts
of the microprocessor because it is in charge of the
entire process.
Creates control signals that tell the Arithmetic
Logic Unit (ALU) and the Registers how to
operate, what to operate on, and what to do
with the result.
The Control Unit makes sure everything happens
in the right place at the right time.
6. 3. REGISTER SET
Use to complete the tasks the Control Unit has
requested
The data can come from the data cache, main memory, or
the control unit, and are all stored at special locations within
the Registers.
7. 4. ACCUMULATOR
The accumulator stores the
result of every ALU
operation, and is also one of
the operands to every
instruction. This means that
our ISA can be less
complicated, because
instructions only need to
specify one operand, instead
of two operands and a
destination
8. 5. CONDITION CODE REGISTER
The code register is a hardware register which contains
information about the state of the processor. Individual bits
are implicitly or explicitly read and/or written by the machine
code instructions executing on the processor
9. COMMON FLAG
This is a list of the most common CPU status register flags, implemented in
almost all modern processors.
Flag Name Description
Z Zero flag Indicates that the result of an arithmetic or logical operation (or,
sometimes, a load) was zero.
C Carry flag Enables numbers larger than a single word to be added/subtracted
by carrying a binary digit from a less significant word to the least
significant bit of a more significant word as needed. It is also used to
extend bit shifts and rotates in a similar manner on many processors
(sometimes done via a dedicated X flag).
S / N Sign flag
Negative flag
Indicates that the result of a mathematical operation is negative. In
some processors,[the N and S flags are distinct with different
meanings and usage: One indicates whether the last result was
negative whereas the other indicates whether a subtraction or
addition has taken place.
V / O / W Overflow flag Indicates that the signed result of an operation is too large to fit in
the register width using twos complement representation.
10. COMMON FLAG
This is a partial list of other, less common status flags that various CPUs
support.
Flag Name Description
H / A Half-carry flag
Auxiliary flag
Decimal adjust flag
Indicates that a bit carry was produced between the
nibbles (typically between the 4-bit halves of a byte
operand) as a result of the last arithmetic operation.
Such a flag is generally useful for
implementing BCD arithmetic operations on binary
hardware.
P Parity flag Indicates whether the number of set bits of the last
result is odd or even.
I Interrupt flag Indicates that an interrupt is currently active, and
that the currently executing code is part of
an interrupt handler routine.
S Supervisor flag Indicates that CPU is operating in supervisor mode,
having enhanced permissions enabled and access
to special instructions typically reserved for the
operating system itself, as opposed to the normal
"user" instruction set.
11. 6. PROGRAM COUNTER
The Program
Counter (PC) is a
register structure that
contains the address
pointer value of the
current instruction. Each
cycle, the value at the
pointer is read into the
instruction decoder and
the program counter is
updated to point to the
next instruction
12. EXAMPLES
MIPS
The MIPS architecture uses a byte-addressable instruction
memory unit. MIPS is a RISC computer, and that means that
all the instructions are the same length: 32-bits. Every cycle,
therefore, the PC needs to be incremented by 4 (32 bits = 4
bytes).
Intel IA32
The Intel IA32 (better known by some as "x86") is a CISC
architecture, which means that each instruction can be a
different length. The Intel memory is byte-addressable. Each
cycle the instruction decoder needs to determine the length
of the instruction, in bytes, and it needs to output that value
to the PC. The PC unit increments itself by the value
received from the instruction decoder.
13. BRANCHING
Non Offset Branching
- A non-offset branch, frequently referred to as a "jump" is a branch
where the previous PC value is discarded and a new PC value is loaded
from an external source.
14. BRANCHING
Offset Branching
- An offset branch is a branch where a value is added (or subtracted) to
the current PC value to produce the new value. This is typically used in
systems where the PC value is larger then a register value or an
immediate value, and it is not possible to load a complete value into the
PC
15. 7. STACK POINTER
A stack pointer is a small register that stores the address of the
last program request in a stack.
A stack (also called a pushdown stack) operates in a last-in/first-out
sense. When a new data item is entered or "pushed" onto the top of a
stack, the stack pointer increments to the next physical memory
address, and the new item is copied to that address
17. DATA BUS
it is used to transfer data within Microprocessor and
Memory/Input or Output devices.
It is bidirectional as Microprocessor requires to send or
receive data.
The data bus also works as address bus when multiplexed
with lower order address bus. Data bus is 8 Bits long.
18. ADDRESS BUS
used to transfer the addresses of Memory or I/O
devices.
It is unidirectional.In Intel 8085 microprocessor, Address bus
was of 16 bits.
This means that Microprocessor 8085 can transfer
maximum 16 bit address which means it can address
65,536 different memory locations.
This bus is multiplexed with 8 bit data bus
19. CONTROL BUS
to process data, that is what to do with the selected
memory location.
Some control signals are Read, Write and Opcode fetch etc.
Various operations are performed by microprocessor with
the help of control bus.
This is a dedicated bus, because all timing signals are
generated according to control signal.
20. CLOCK SYSTEM
The 8085 incorporates all of the features that the 8224 clock
generator and 8228 system controller provided for the 8080A
X1 and X2: Are connected to a crystal, LC or RC network to
drive the internal clock generator. The input frequency is
divided by 2 to give the processor's internal operating
frequency.
CLK: Clock output for use as a system clock. The period of CLK
is twice the X1, X2 input period.
8085 clock system
21. INTEL 8085 MICROPROCESSOR FAMILY
Previous
Generation
Related Family Next Generation
•8080
» 8-bit
microprocessor
•» Up to 4 MHz
•» 64 KB RAM
•» Stack in RAM
•» 256 I/O ports
40-pin DIP
•8085
» 8-bit
microprocessor
•» Up to 8 MHz
•» 64 KB RAM
•» Single voltage
•» On-chip
peripherals
•» 256 I/O ports
•» 8080 object-
code compatible
40-pin DIP
44-pin PLCC
•Z80
» Up to 33 MHz
•» 8080 emulation
mode
•8086
» 16-bit
microprocessor
•» 16-bit data bus
•» Up to 10 MHz
•» 1 MB RAM
•» 64K I/O ports
40-pin DIP
56-pin QFP
44-pin PLCC
22. CLOCK SYSTEM
6008 clock system
It comes in a 40-pin package that requires additional elements to make
up a
useful circuit. The normal clock signal speed is 1MHz, though the 6800
does
not have an internal clock, ROM or RAM.
The 6800 has an 8-bit word size for instructions and data
The 6800 requires a two phase clock to operate.
The address bus is 16-bit allowing the microprocessor to access 64k 8-bit
words in memory (Locations from 0000 to FFFF).
23. INTEL 6008 MICROPROCESSOR FAMILY
6802
The 6802 contains the 6800 CPU with the
addition of 128 bytes of RAM for real time
scratch pad operations.
The RAM is given the addresses 0000 to 007F
so direct addressing can be used on it. There
are 2048 bytes of ROM for program storage and
an on-board clock. The 6802 uses the same
instruction set as he 6800.
24. INTEL 6008 MICROPROCESSOR FAMILY
6805
The 6805 was a cheaper version of the
6803. It dropped some of the less used
instructions to simplify operation.
6809
The 6809 extended the 6800 capability into
16-bit applications, but it wasn't a true 16-bit
microprocessor. The additional functionality
was achieved by including extra registers,
addressing facilities and instructions. The
internal data buses were expanded to 16-
bits