9. VYATTA USERS MEETING Autumn 2013
ハードウェアの中身は分からなくもOK
9
FPGA
設定,制御
結果
cmdcmdcmdcmd
addraddraddraddr
lenlenlenlen
data data data data
data data data data
∼∼ ∼∼
data data data data
data data data data
∼∼ ∼∼
0x01: result read
0x21: config read
0x22: config write
0x31: start
0x32: running?
write_target_list(list)
start_ping_counter()
wait_ping_counter()
read_result
(UDP)