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Part 1 Computer Systems Hardware (Book No. 1 Chapter 2)
HARDWARE ,[object Object],[object Object],[object Object],[object Object],[object Object]
Introduction Functions of hardware in a computer can be divided into five main units
Five Main Units in Computing ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
5 main units of computers Input Unit Main Storage Unit Output Unit Arithmetic Unit Control Unit Processor (CPU) Data Flow Control Flow
2.1 Information Element ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IC ,[object Object],[object Object]
Integrated Circuit ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IC Classification > 10 5 VLSI (Very Large Scale Integration) 10 3  – 10 4 LSI (Large Scale Integration) 10 2  – 10 3 MSI (Medium Scale Integration) 10 1  – 10 2 SSI (Small Scale Integration) Integration Level IC
Transistors Per IC
Fujitsu Integrated Circuits 86903-33   Full die shot of the Fujitsu 86903-33 showing the complete pad ring using oblique illumination with blue, red, and yellow gels.
Sun Microsystems Integrated Circuits UltraSPARC ,[object Object]
Intel Integrated Circuits i4004 ,[object Object]
Semiconductor Memory ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
RAM ,[object Object],[object Object],[object Object],[object Object],[object Object]
RAM ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SRAM ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
DRAM (Dynamic RAM) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SDRAM (Synchronous DRAM) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
RDRAM ,[object Object],[object Object],[object Object],[object Object],[object Object]
VRAM ,[object Object],[object Object],[object Object]
Other Types of RAM ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
ROM (Read Only Memory) ,[object Object],[object Object],[object Object],[object Object]
5 Basic Types of ROM ,[object Object],[object Object],[object Object],[object Object],[object Object]
ROM ,[object Object],[object Object],[object Object],[object Object]
PROM ,[object Object],[object Object],[object Object]
PROM ,[object Object],[object Object],[object Object]
EPROM ,[object Object],[object Object],[object Object],[object Object],[object Object]
EEPROM ,[object Object],[object Object],[object Object],[object Object]
Flash Memory ,[object Object],[object Object],[object Object]
Processor Architecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Processor Structure ,[object Object],[object Object]
Processor Structure ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Clock Speed
Von Neumann Architecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
 
Sequential control system
Processor Structure ,[object Object],[object Object],[object Object],[object Object]
ALU
Processor operation principles ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Processor Insight Instruction 1 Instruction 2 Read/write controller Address decoder Main Storage Unit ALU GR 0 GR 1 GR 2 GR n Instruction decoder Operation Address +1 Control unit Arithmetic unit PC IR Control bus Address bus Data bus Processor Base Address Flag PSW Index Complement
Executing Program ,[object Object],[object Object],[object Object]
Executing Program ,[object Object],[object Object],[object Object]
Clock ,[object Object],[object Object]
Silicon Structure Fetch Logic Decode/dispatch L2 cache L1 cache Vector Processing Unit Floating Point Unit Arithmetic Logic Unit Load / Store Unit Retire and write-back logic Memory Management Unit Branch Processing Unit FETCH DECODE EXECUTE RETIRE
Processor operation principles Instruction readout and decoding ,[object Object],[object Object],[object Object]
Processor operation principles Instruction readout and decoding ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Processor operation principles Instruction readout and format ,[object Object],[object Object],[object Object],[object Object],[object Object],Instruction e.g. HALT
Processor operation principles Instruction readout and format ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Instruction Address e.g. INC GR1 Instruction Address Address e.g. MOV GR1, X Instruction Address Address Address e.g. MUL GR3, GR2, GR1
Processor operation principles Instruction Readout
Processor operation principles Instruction Decoding ,[object Object],[object Object],[object Object]
Processor operation principles Instruction Decoding
Processor operation principles Instruction Decoding
Processor operation principles Instruction Execution ,[object Object]
Processor operation principles Instruction Execution ,[object Object],[object Object],[object Object],[object Object]
Processor operation principles Instruction Execution ,[object Object]
Processor operation principles Instruction Execution ,[object Object]
Processor operation principles Instruction Execution ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Processor operation principles Instruction Execution ,[object Object]
Processor operation principles Instruction Execution ,[object Object]
Processor operation principles Registers ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Register Program Counter (PC) ,[object Object],[object Object],[object Object]
Register  Accumulator ,[object Object],[object Object],[object Object],[object Object]
Register Index Register ,[object Object],[object Object]
Register Base register ,[object Object]
Register Flag register ,[object Object]
Register Program Status Word (PWS) ,[object Object],[object Object]
Register Complement Register ,[object Object]
Address specification mode ,[object Object],[object Object],[object Object],[object Object]
Address specification mode ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Immediate Specification ,[object Object]
Direct address specification ,[object Object]
Index address specification ,[object Object],[object Object]
Register Address Specification ,[object Object],[object Object]
Base address specification ,[object Object],[object Object]
Relative address specification ,[object Object]
Indirect address specification ,[object Object],[object Object]
Processor operation principles ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
I-Cycle and E-Cycle
Speed performance enhancement in Processor ,[object Object],[object Object],[object Object],I-Cycle E-Cycle
Sequential processing Pipeline  processing
Instruction Set ,[object Object],[object Object],[object Object],Complex Instruction Set Computer (CISC) ,[object Object],[object Object],[object Object],Reduced Instruction Set Computer (RISC)
Parallel method ,[object Object],[object Object],[object Object]
Parallel method
Multi-processor ,[object Object],[object Object],[object Object],[object Object]
Parallel Processing ,[object Object],[object Object],Instruction 1 F D E R Instruction 3 F D E R Instruction 5 F D E R Instruction 2 F D E R Instruction 4 F D E R Instruction 6 F D E R Instruction 1 F' F" D' D" E' E" R' R" Instruction 2 F' F" D' D" E' E" R' R" Instruction 3 F' F" D' D" E' E" R' R" Instruction 4 F' F" D' D" E' E" R' R" Instruction 5 F' F" D' D" E' E" R' R" Instruction 6 F' F" D' D" E' E" R' R"
Multi-processor ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Parallel Processing ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Processor Performance ,[object Object],[object Object],[object Object],[object Object],[object Object]
Digital IC NOT gate AND gate OR gate XOR gate NAND gate NOR gate Half-adder Full-adder Flip-flop Digital IC Logic Gates Transistors Capacitors Diodes
' NOT '  Gate 0 1 1 0 NOT  A A A
' AND '  Gate 1 1 1 0 0 1 0 1 0 0 0 0 A  AND  B B A A B
' OR '  Gate 1 1 1 1 0 1 1 1 0 0 0 0 A  OR  B B A A B
'X OR '  Gate 0 1 1 1 0 1 1 1 0 0 0 0 A  XOR  B B A A B
'N AND '  Gate 0 1 1 1 0 1 1 1 0 1 0 0 A  NAND  B B A A B
'N OR '  Gate 0 1 1 0 0 1 0 1 0 1 0 0 A  NOR  B B A A B
Exercise 1 ,[object Object],A B C 1 1 1 0 0 1 0 1 0 1 0 0 C B A
Exercise 2 ,[object Object],a 1 a 0 L 1 L 2 L 3 L 4 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 L 4 L 3 L 2 L 1 a 0 a 1
Exercise 3 ,[object Object],S A B C 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 0 1 0 1 0 0 0 0 C S B A
Hardware Storage
Memory Architecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Memory Capacity and Performance ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Memory Hierarchy Structure
Memory Hierarchy Structure
Memory Capacity
Memory Performance (Access Time) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Memory Performance (Cycle Time) ,[object Object],[object Object],[object Object],[object Object]
Cycle Time
Memory Configuration ,[object Object],[object Object],[object Object]
Error Correcting Codes (ECC) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
ECC ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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