2. 1 Introduction
The purpose of this lab is to use the theory of the boost converter to build one. This lab report
will focus on the design, simulation, and some hardware testing for the openloop version, which
would include calculations and measurements to extract values necessary for the design.
Similarly, the same process will occur for the closed loop boost converter, which will require
different set of tests to prove that the proposed design is sufficient for the specifications.
1.1 Design Specifications
a) Input voltage: 12V DC
b) Output voltage: 20V DC
c) Minimum Load: 10W
d) Maximum Load: 20W
e) Maximum Ripple voltage: 2 Vpp (based on output specs)
g) Converter frequency: 100 kHz
h) Inductor Value: 50 uH
2 PreSimulation Parameter Calculations
2.1 Inductor Value Selection
This lab provides us with a inductor value to work with. This part will be used later for the
hardware part of the lab. Using the following equation below, the number of copper wiring turns
for the core was found:
17 turns N =
√ L
Al =
√163 10*
−9
50 10*
−6
=
The end calculations presented that a 17 copper wire turns for the core was needed to create a
50uH inductor.
2.2 Capacitor Value Selection
Using the same parameters given in Table 1 and the delta inductor current, the following
equation was used to find the capacitance value needed:
≥ μF C ΔV f0 s
I Doutmax
= 2(100k)
0.2 0.75* = 2
3. With the given equation above, the design needed a capacitor value of at least 2 F in parallel μ
with the load. However, to meet transient and output voltage requirements, we used a
capacitance value of 127 uF (33+47+47 uF capacitances).
3 OpenLoop Boost Converter
The first series of the lab test both the simulated and the physical hardware openloop circuit
design:
3.1 Input for the MOSFET Gate
The input to the MOSFET Gate is controlled by the SG3524 IC PWM. The schematic in Figure 1
was used below.
Figure 1. General Test Schematic of SG3524 Test Circuit
The RT and CT parameters are used to control the switching frequency of the oscillator. The
relationship of this switching frequency is as follows:
(in kHz) fs = 1.30
R CT T
in kΩRT
in μFCT
4.
Practical values of RT values fall between 1.8kΩ and 100kΩ so for the design, which requires
the switching frequency to be 100kHz. Thus, RT was chosen to be 10kΩ, which made CT be
0.013 uF.
Additionally, pins 4 and 5 were grounded since the current limit option was not used and pins 3
and 10 were left open since they were also not used in the circuit.
The resulting waveform of this PWM is shown in Figure 2, which shows that the switching
frequency is near 100 kHz:
Figure 2. Output of the PWM
Using the potentiometer that is inputted into pin 2 of the SG3524, the duty cycle can be adjusted
by the changing voltage in the voltage divider. In the case in Figure 2, the output was outputting
16 V for 43.5% of the time for every switching cycle.
3.2 OpenLoop Design
Figure 3 is the open loop boost converter design that will be built in this lab. The gate of the
MOSFET is connected to a SG3524, which is a PWM that controls the switching frequency and
the input voltage into the gate.
5.
Figure 3. Open Loop Boost Converter Design (using Multisim)
Because the SG3524 is not in the Multisim database, a pulse wave generator from the simulation
was used instead for the simulation tests.
4 Simulation/Hardware Tests and Calculations (OpenLoop)
Before building the actual hardware for the lab, some tests had to be run through Multisim to
ensure that our design has met the specifications for this lab.
4.1 Varying Load Current
Figure 4. Transient Analysis of the Boost Converter at different currents
6. For the first set of tests, the load current was varied by putting in different load resistors ranging
from 20 Ω to 40 Ω. By observing the plots, the steadystate DC voltage is approximately 20V
and the voltage ripples are within specifications as shown in Figure 3 with slight variations in the
DC voltage.
4.2 Simulation Half Load Analysis
The following simulation tests were run at half load or 15W, which would mean that our load
resistor is at 26.67 Ω.
4.2.1 Inductor Current
Figure 5. Transient Analysis of the Inductor Current at halfload
Figure 5 shows the plot of the inductor current with respect to time. As shown in the figure,
when the MOSFET is on, the inductor current increases while the inductor is charging. Then
when the MOSFET is off, the voltage discharges to the capacitor/load, decreasing the inductor
current during this cycle.
4.2.2 Switch Voltage
Figure 6. Transient Analysis of the Switch Voltage.
7. Figure 6 above shows the Vds of the MOSFET. The voltage oscillates between 0 and 20 V in
steady state. In steady state, when the MOSFET is on and the gate voltage is high (16 V), Vds =
0 V due to the fact that the MOSFET becomes a short circuited wire. Then when the MOSFET is
off, the MOSFET becomes an open circuit and has a voltage drop equal to the voltage across the
output plus the voltage across the diode.
4.2.3 Switch Current
Figure 7. Transient Analysis of the switch current.
Figure 7 above shows the drain and source current of the MOSFET. When the MOSFET is on,
the current has a sawtoothlike waveform. This is so because inductor is building up voltage
through magnetic field when the MOSFET is in its on state. Because of the short circuit behavior
of the MOSFET, the current waveform through the MOSFET is similar as that of the inductor.
Then when the MOSFET is off, the current is zero because the MOSFET is in an open circuit
state.
8. 4.3 Hardware HalfLoad Analysis
The following hardware tests were run at half load or 15W, which would mean that our load
resistor is at 26.67 Ω.
4.3.1 Inductor Current
Figure 8. Transient Analysis of the Voltage across the shunt resistor below the 12 V source.
Using a shunt 0.1 Ω below the 12 V power source, the voltage waveform of the 0.1 Ω resistor is
given as shown in Figure 8. The waveform is giving negative values because the shunt resistor
was placed below the power supply with the positive end of the oscilloscope placed on the
negative end of the 12 V power supply. Dividing the waveform in Figure 8 by 0.1 will give the
inductor current waveform. Additionally, the shape of waveform is similar to the simulation
waveforms, which also exhibit a triangular wave.
9. 4.3.2 Switch Voltage
Figure 9. Transient Analysis of the Vds of the MOSFET.
Figure 9 shows the Vds of the MOSFET. This waveform is very similar to the simulation
waveforms. Both Vds jump to at least 20 V in steady state when the MOSFET turns off because
the MOSFET is in an open circuit state. Then the voltage drops to 0 V when the MOSFET turns
on.
4.3.3 Switch Current
Figure 10. Transient Analysis of the Voltage across the shunt resistor below the source of the MOSFET.
10. Figure 10 shows the voltage waveform of the shunt 0.1 Ω resistor placed below the source of the
MOSFET. Dividing this waveform by 0.1 will give the switch current waveform (drain and
source current). This shape of the waveform is also similar to that of the simulation’s. Both have
zero current when the MOSFET is off and then when the MOSFET is on, the current exhibit
sawtoothlike waveform similar to that of the inductor current.
4.3.4 Power Loss Via Switching (MOSFET)
Using the waveforms and values from the current in the previous sections, the estimated power
loss from the MOSFET switching were found. From the MTP3055 Datasheet, the average
switching characteristics were the following:
urn On Delay Time .5 nsT : tON = 8
urn Off Delay Time 3.5 nsT : tOFF = 2
Using these values, the switching losses when MOSFET turns on and turns off using the
following assuming that the Vds and the drain current increased and decreased linearly for
switching events:
OFF to ON (Turn ON):
:verage Current .5 .5A : 0 * 1 0.75 A
:verage V oltage .5 2A : 0 * 2 11.0 V
:ower Losses vg Current Avg V oltageP : A * * tON * fS 0.007 W
ON to OFF (Turn OFF):
:verage Current .5 .08A : 0 * 2 1.04 A
:verage V oltage .5 2A : 0 * 2 11.0 V
:ower Losses vg Current Avg V oltageP : A * * tOFF * fS 0.0268 W
otal Power Loss (PowerOn PowerOff)T : + : 0.0338 W
The power losses were found by finding the average current voltage through switching events for
the short delay times. Then multiply the switching frequency and the time delay for respective on
and off cycle in order to find the total power loss from switching.
11.
4.3 CCM & DCM Mode Operation
Figure 11. Transient Analysis of the Output Voltage at Different Loads (20, 15, 10 W Load Respectively)
At low loads (10 W), the DCM was able to be observed through the output waveform (along
with the Vds waveform). At the very right waveform of Figure 11, the latter (right side) part of
the waveform where duty ratio is in the off section has a dip in the output voltage. This is due to
the low current of the inductor. At higher loads like in the first and second waveforms of Figure,
DCM is rarely seen because the inductor current is high enough for the current to continue drop
for the full duration when the duty cycle is in its off state.
The DC values at different loads are as follows in Table 1:
Table 1: DC voltages based off of Figures 11
Load (W) Average Voltage (DC)
10 (40.0 Ω) 22.0 V
15 (26.6 Ω) 21.5 V
20 (20.0 Ω) 20.4 V
12.
Figure 12. Output Voltage with respect to the load (W)
Figure 12 shows the output voltage with respect to the load. From this plot, the output voltage
decreases as the load increases. From this the range of the output is 2V with the given range of
the load.
4.4 Efficiency
The values below are taken by observation from the waveforms and efficiency values were then
calculated based on the current and voltage values for high and low load:
4.4.1 High Load
vg(V in) a : 12.0V
vg(I(in)) bs(1.48 .24)/2 a = a + 3 : 2.36A
vg(V out) a : 20.4V
vg(I(out)) 0.4/20 a = 2 : 1.02A
vg(P(in)) vg(I(in)) vg(V (in)) a = a * a : 28.3 W
vg(P(out)) vg(I(out)) vg(I(out)) a = a * a : 20.8 W
fficiency avg(P(out))/avg(P(in)) E = : 73.4%
4.4.2 Low Load
vg(V in) a : 12.0V
vg(I(in)) bs(0.70 .90)/2 a = a + 1 : 1.30A
13. vg(V out) a : 22.0V
vg(I(out)) 2/40 a = 2 : 0.55A
vg(P(in)) vg(I(in)) vg(V (in)) a = a * a : 15.6 W
vg(P(out)) vg(I(out)) vg(I(out)) a = a * a : 12.1 W
fficiency avg(P(out))/avg(P(in)) E = : 77.6%
5 ClosedLoop Boost Converter
With the openloop analysis complete, the following simulation and hardware tests were done for
the closedloop version of the boost converter:
5.1 Dynamic Average and Linearization Model
Figure 13. Average Model Circuit of the Boost Converter
Figure 13 is the average model circuit of the boost circuit. Using this circuit, the bode plots of the
transfer function was obtained and shown on Figure 14 and Figure 15, which will be used later in
order to find the parameters for the 2K controller of the closedloop boost converter.
14.
Figure 14. Magnitude Plot of the Average Model Circuit
Figure 15. Phase Plot of the Average Model Circuit
5.4 Transfer Function of Output Voltage Sensor/PWM
Because the PWM duty cycle is dependent on the voltage at pin 9 and its pin 9 voltage ranges
from specifications are from 1.0 V to 3.5 V, the transfer is as the following:
.4 GPWM = 1
3.5−1 = 0
5.5 K Factor Method (2K)
For the 2K Factor Method, we used the following given values from the specifications and
chosen values from the bode plots to calculate the transfer function of the controller circuit. Note
that for every results that follows for each equation is based off of the chosen/given parameters:
Desired Phase Margin: 35 degrees
Cross Frequency: 1360 Hz
15. Power Stage Gain: 31.20 dB
PWM Gain: 0.4
k Feedback: 0.125
Using these values from the bode plots, the following equation was used to find the phase boost
and the K factor:
PM 80 0 ϕboost = − 1 − ϕcross + 9
tan( 5) K = 2
ϕcross
+ 4
With the K factor, we are then able to find the pole and zero frequency using the following
equations:
2πf /K wZero = cr
2πf wPole = cr * K
Then using the feedback constant, the PWM gain, and the power stage gain, the desired
compensator gain at crossover frequency was found using the following equation (note all of
these terms are linear magnitude gains):
Gcr = 1
k G Gfb PWM PS
Additionally, the controller gain was found using the zero frequency and the desired kc
compensator gain in following equation:
G w kc = cr Zero
Using the calculated parameter values, the transfer function for a 2K was used in the following
equation format:
Gc = s
kc (1+s/wz)
(1+s/wp)
With all the values needed, the two capacitance values and the resistance value of the controller
(shown on Figure x) using the following equations:
C1 = k wc P
g wm Z
C2 = kc
gm
− C1
R = 1
w CZ 2
16.
Figure 16. 2K Factor Controller
With everything calculated and compiled together, the 2K controller is ready to be built into the
closedloop boost converter design. The following table are the resulting values from the
equation:
Table 2: Output Voltage readings with respect to changing Vin
Parameter Values
Phase Boost 75.5 degrees
wZero 1070 rad/s
wZero 67824 rad/s
Desired Gcr 0.55 (linear gain)
kc 593.24
C1 53.5 nF
C1 33.7 uF
R 280 Ω
Note: DISREGARD any of the controller circuit element values in the future figures as they are
just there as placeholders to know where the circuit elements are inserted. Most of the results
were taken using values near the calculated values from small tweaks and trialanderror.
17. 5.6 Feedback Design in MULTISIM
Figure 17 below is the feedback design of the closedloop boost converter and Figure 18 is the
transient analysis of this feedback design.
Figure 17. Feedback Design of ClosedLoop Boost Converter
Figure 18. 2K Factor Controller
The transient analysis shows that although there is a bit of spiking in the output voltage, in steady
state, the output voltage maintains to 20 V, which shows that the calculated feedback controller
is sufficient.
18. 5.6 ClosedLoop Boost Converter Design
Figure 19. Complete ClosedLoop Converter Design
Figure 19 shows the complete design of the closedloop boost converter. This design consists of
the modified openloop portion, the controller, feedback loop, and the MOSFET driver. The
controller is connected to pin 9 of the SG3524. The feedback loop is connected from the output
of the boost in parallel with a voltage divider, which is connected to pin 1. The design also has a
slow start feature placed at pin 2 of the SG3524, which is just a capacitor in parallel with the
resistor.
5.7 Steady State VOLTAGE Regulation
For the first series of tests, the steady state voltage regulation had to be observed. The input
voltage varied from 10 to 14 V at load of 15 W (26.6 Ω) in order to observe the effect on the
output voltage:
Table 3: Output Voltage readings with respect to changing Vin
Vin (V) Vout (V)
10.0 19.50
10.5 19.67
11.0 19.74
19. 11.5 19.80
12.0 19.86
12.5 19.91
13.0 19.96
13.5 20.01
14.0 20.03
Figure 20: Output voltage versus Input Voltage of the ClosedLoop Boost Converter
This plot from Figure 20 shows that even with the input voltage changes, the range for the output
voltage from the input voltage changes from 10 to 14 V is 0.53 V, which is minor. This would
show that the DC voltage doesn’t drop dramatically for the output voltage for any minor changes
in input, which shows that this design is sufficient and stable.
21. 20 (20.0 Ω) 19.43
Figure 22: Output Voltage versus Different Loads
The plot in Figure 22 for the closedloop design shows a similar behavior for the openloop
design that for increasing loads, the average DC output voltage decreases. Although both exhibit
same plot behaviors, the closedloop converter shows less change and smaller range of output
voltage change near 20 V. Specifically, the range of the DC voltage for the openloop for the
given loads is 2 V while the range is 0.8 V for that of the closedloop, which shows less
variations and more stability from load changes.
6 Conclusion
With hardware and simulation tests for the openloop, we were able to create both the openloop
and closedloop version of the boost converter. First calculations and test had to be done for the
respective circuits. After passing the tests, then the hardware was then able to be built and tested.
Some tweaks had to be done in order to pass specifications of the lab. Overall, the lab has
enabled us to learn major and minor specs of the boost converter in order to build one.
