Kevin Townsend

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I currently work at the Reconfigurable Computing Laboratory at Iowa State University, where I research ways to accelerate applications with FPGAs. Applications I have designed accelerators for include exact DNA alignment, sequential belief propagation, sparse matrix vector multiplication and k nearest neighbors. FPGAs are the chameleons of the chip world. To accelerate an application I create a processor design. Electronic design tools then turn this processor design into a schematic the FPGA can read and then emulate the processor. From my view, I now have the processor I want. (Although it's a bit slower than a processor made in a ASIC Fab.)

bag of words text classification k-nn fpga floating point compression fzip convey high performance reconfigurable computing

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Kevin Townsend

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First Place Memocode'14 Design Contest Entry

Floating Point Compression EIT'15

k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator EIT'15

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