2. Kouji Matsui - kekyo
• NAGOYA city, AICHI pref., JP
• Twitter – @kekyo2 / Facebook
• ux-spiral corporation
• Microsoft Most Valuable Professional VS
and DevTech 2015-
• Certified Scrum master / Scrum product
owner
• Center CLR organizer.
• .NET/C#/F#/IL/metaprogramming or like…
• Bike rider
3. Agenda
•Physical side scales
•Logical side scales
•Data stream between physicals and logicals
•Locality of reference
•Anti-locality of reference
•Conclusion
8. Physical side scales
The “cache memory” bind at the fixed CPU/Core
(Non configurable)
The “shared cache memory” bind at the fixed
CPU/Core
(Non configurable)
9. Agenda
•Physical side scales
•Logical side scales
•Data stream between physicals and logicals
•Locality of reference
•Anti-locality of reference
•Conclusion
10. Logical side scales
Process #1
Virtual
Memory
Space
Thread #1
Thread #1
Thread #1
Thread #1
Thread #1
Process #2
Virtual
Memory
Space
Thread #1
Thread #1
Thread #1
Thread #1
Thread #11
Process #3
Virtual
Memory
Space
Thread #1
Thread #1
Thread #1
Thread #1
Thread #21
Process #4
Virtual
Memory
Space
Thread #1
Thread #1
Thread #1
Thread #1
Thread #31
Process #5
Virtual
Memory
Space
Thread #1
Thread #1
Thread #1
Thread #1
Thread #41
13. Agenda
•Physical side scales
•Logical side scales
•Data stream between physicals and logicals
•Locality of reference
•Anti-locality of reference
•Conclusion
17. Agenda
•Physical side scales
•Logical side scales
•Data stream between physicals and logicals
•Locality of reference
•Anti-locality of reference
•Conclusion
22. Agenda
•Physical side scales
•Logical side scales
•Data stream between physicals and logicals
•Locality of reference
•Anti-locality of reference
•Conclusion
23. Thread #1
Thread #1
Thread #1
Thread #1
Thread #21
Thread #1
Thread #1
Thread #1
Thread #1
Thread #31
Thread #1
Thread #1
Thread #1
Thread #1
Thread #41
Logical Core #4
Logical Core #3
L1/L2 cache #3
L1/L2 cache #4
L3 cache #2
NUMA node bound memory
Common value
Common value
Common value
Load/Preload
Load/Preload
These threads access
common value
24. Thread #1
Thread #1
Thread #1
Thread #1
Thread #21
Thread #1
Thread #1
Thread #1
Thread #1
Thread #31
Thread #1
Thread #1
Thread #1
Thread #1
Thread #41
Logical Core #4
Logical Core #3
L1/L2 cache #3
L1/L2 cache #4
L3 cache #2
NUMA node bound memory
Common value
Common value
Common value
Race condition
(Receive coherence penalty)
STRATEGY:
• Turn to immutable
• Hashed indexer
Writeback
Writeback
25. Agenda
•Physical side scales
•Logical side scales
•Data stream between physicals and logicals
•Locality of reference
•Anti-locality of reference
•Conclusion
26. Conclusion
The execution context bounds not THREAD. The code executor is
CPU CORE.
CPU cores have structuable nested cache system.
Cache miss penalty is large.
Cache coherency penalty is large.
Both I/O systems too.
Important cache-related architecture:
◦ Locality of reference
◦ Immutable
27. Thanks join!
My blog
◦ http://www.kekyo.net/
Current active project:
◦ IL2C - A translator implementation of .NET intermediate language to C
language.
◦ YouTube: http://bit.ly/2xtu4MH
◦ GitHub: https://github.com/kekyo/IL2C